SIRegisterInfo.cpp File Reference

SI implementation of the TargetRegisterInfo class. More...

#include "SIRegisterInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUSubtarget.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "AMDGPURegAsmNames.inc.cpp"

Include dependency graph for SIRegisterInfo.cpp:

Go to the source code of this file.

Macros
#define	AMDGPU_REG_ASM_NAMES
#define	REG_RANGE(BeginReg, EndReg, RegTable)

Functions
static bool	hasPressureSet (const int *PSets, unsigned PSetID)
static unsigned	findPrivateSegmentWaveByteOffsetRegIndex (unsigned RegCount)
static unsigned	getNumSubRegsForSpillOp (unsigned Op)
static int	getOffsetMUBUFStore (unsigned Opc)
static int	getOffsetMUBUFLoad (unsigned Opc)
static bool	buildMUBUFOffsetLoadStore (const SIInstrInfo *TII, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
static std::pair< unsigned, unsigned >	getSpillEltSize (unsigned SuperRegSize, bool Store)

Variables
static cl::opt< bool >	EnableSpillSGPRToSMEM ("amdgpu-spill-sgpr-to-smem", cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"), cl::init(false))
static cl::opt< bool >	EnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))

Detailed Description

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

Macro Definition Documentation

AMDGPU_REG_ASM_NAMES

#define AMDGPU_REG_ASM_NAMES

REG_RANGE

#define REG_RANGE	(		BeginReg,
			EndReg,
			RegTable
	)

Value:

if (Reg >= BeginReg && Reg <= EndReg) {                \
      unsigned Index = Reg - BeginReg;                     \
      assert(Index < array_lengthof(RegTable));            \
      return RegTable[Index];                              \
    }

Referenced by llvm::SIRegisterInfo::getRegAsmName().

Function Documentation

buildMUBUFOffsetLoadStore()

static bool buildMUBUFOffsetLoadStore ( const SIInstrInfo *  TII, MachineFrameInfo &  MFI, MachineBasicBlock::iterator  MI, int  Index, int64_t  Offset  )

static

Definition at line 485 of file SIRegisterInfo.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::BuildMI(), llvm::RegScavenger::FindUnusedReg(), llvm::MDNode::get(), llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterClass::getID(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), getOffsetMUBUFLoad(), getOffsetMUBUFStore(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), llvm::MachineFunction::getSubtarget(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::MachinePointerInfo::getWithOffset(), llvm::RegState::Implicit, llvm::MCInstrDesc::mayStore(), MI, llvm::MinAlign(), Size, llvm::ARM_MB::ST, SubReg, and TII.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

findPrivateSegmentWaveByteOffsetRegIndex()

static unsigned findPrivateSegmentWaveByteOffsetRegIndex ( unsigned  RegCount )

static

Definition at line 118 of file SIRegisterInfo.cpp.

References Reg.

Referenced by llvm::SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg().

getNumSubRegsForSpillOp()

static unsigned getNumSubRegsForSpillOp ( unsigned  Op )

static

Definition at line 394 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

getOffsetMUBUFLoad()

static int getOffsetMUBUFLoad ( unsigned  Opc )

static

Definition at line 450 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

getOffsetMUBUFStore()

static int getOffsetMUBUFStore ( unsigned  Opc )

static

Definition at line 429 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

getSpillEltSize()

static std::pair<unsigned, unsigned> getSpillEltSize ( unsigned  SuperRegSize, bool  Store  )

static

Definition at line 627 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::restoreSGPR(), and llvm::SIRegisterInfo::spillSGPR().

hasPressureSet()

static bool hasPressureSet ( const int *  PSets, unsigned  PSetID  )

static

Definition at line 32 of file SIRegisterInfo.cpp.

References EnableSpillSGPRToSMEM, EnableSpillSGPRToVGPR, llvm::SIRegisterInfo::getRegUnitPressureSets(), llvm::cl::init(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::cl::ReallyHidden, Reg, and llvm::BitVector::set().

Variable Documentation

EnableSpillSGPRToSMEM

cl::opt<bool> EnableSpillSGPRToSMEM("amdgpu-spill-sgpr-to-smem", cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"), cl::init(false))

static

Referenced by hasPressureSet().

EnableSpillSGPRToVGPR

cl::opt<bool> EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))

static

Referenced by hasPressureSet().