15 #ifndef LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H 16 #define LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H 24 #include <initializer_list> 30 class MachineRegisterInfo;
33 class TargetInstrInfo;
34 class TargetRegisterClass;
35 class TargetRegisterInfo;
66 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
158 : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
165 bool isValid()
const {
return BreakDown && NumBreakDowns; }
172 bool verify(
unsigned MeaningfulBitWidth)
const;
196 unsigned NumOperands = 0;
199 assert(i < getNumOperands() &&
"Out of bound operand");
200 return OperandsMapping[i];
214 unsigned NumOperands)
215 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
216 NumOperands(NumOperands) {
218 "Use the default constructor for invalid mapping");
247 OperandsMapping = OpdsMapping;
298 static const int DontKnowIdx;
307 getVRegsMem(
unsigned OpIdx);
313 getNewVRegsEnd(
unsigned StartIdx,
unsigned NumVal)
const;
348 void createVRegs(
unsigned OpIdx);
360 void setVRegs(
unsigned OpIdx,
unsigned PartialMapIdx,
unsigned NewVReg);
375 getVRegs(
unsigned OpIdx,
bool ForDebug =
false)
const;
432 return *RegBanks[
ID];
474 unsigned NumBreakDowns)
const;
490 template <
typename Iterator>
507 std::initializer_list<const ValueMapping *> OpdsMapping)
const;
519 unsigned NumOperands = 0)
const;
526 unsigned NumOperands)
const {
527 return getInstructionMappingImpl(
false, ID, Cost,
528 OperandsMapping, NumOperands);
533 return getInstructionMappingImpl(
true);
613 unsigned Size)
const {
728 const RegisterBankInfo::PartialMapping &PartMapping) {
729 PartMapping.print(OS);
734 operator<<(raw_ostream &OS,
const RegisterBankInfo::ValueMapping &ValMapping) {
735 ValMapping.print(OS);
741 const RegisterBankInfo::InstructionMapping &InstrMapping) {
742 InstrMapping.print(OS);
747 operator<<(raw_ostream &OS,
const RegisterBankInfo::OperandsMapper &OpdMapper) {
748 OpdMapper.print(OS,
false);
754 hash_code
hash_value(
const RegisterBankInfo::PartialMapping &PartMapping);
758 #endif // LLVM_CODEGEN_GLOBALISEL_REGISTERBANKINFO_H void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
This class represents lattice values for constants.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
class llvm::RegisterBankInfo *void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getCost() const
Get the cost.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned getNumRegBanks() const
Get the total number of register banks.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
SmallVector< const InstructionMapping *, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
bool isValid() const
Check if this ValueMapping is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
unsigned const TargetRegisterInfo * TRI
virtual ~RegisterBankInfo()=default
unsigned getID() const
Get the ID.
void dump() const
Print this partial mapping on dbgs() stream.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const ValueMapping & getOperandMapping(unsigned i) const
Get the value mapping of the ith operand.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank)
Provide a shortcut for quickly building PartialMapping.
bool verify() const
Check that the Mask is compatible with the RegBank.
static int getID(struct InternalInstruction *insn, const void *miiArg)
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
const TargetRegisterClass & getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
const RegisterBank * RegBank
Register bank where the partial value lives.
TargetInstrInfo - Interface to description of machine instruction set.
ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
Initialize a ValueMapping with the given parameter.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
unsigned NumRegBanks
Total number of register banks.
ValueMapping()
The default constructor creates an invalid (isValid() == false) instance.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
unsigned getHighBitIdx() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
const PartialMapping * end() const
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
MachineInstr & getMI() const
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
This class implements the register bank concept.
Helper struct that represents how a value is mapped through different register banks.
A range adaptor for a pair of iterators.
const PartialMapping * begin() const
Iterators through the PartialMappings.
unsigned getID() const
Get the ID.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
InstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands)
Constructor for the mapping of an instruction.
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned NumBreakDowns
Number of partial mapping to break down this value.
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const RegisterBank & getRegBank(unsigned ID) const
Get the register bank identified by ID.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
This class implements an extremely fast bulk output stream that can only output to a stream...
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
RegisterBankInfo()
This constructor is meaningless.
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
unsigned getNumOperands() const
Get the number of operands.
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
RegisterBank ** RegBanks
Hold the set of supported register banks.
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.