| enum | llvm::AArch64ISD::NodeType : unsigned {
llvm::AArch64ISD::FIRST_NUMBER = ISD::BUILTIN_OP_END,
llvm::AArch64ISD::WrapperLarge,
llvm::AArch64ISD::CALL,
llvm::AArch64ISD::TLSDESC_CALLSEQ,
llvm::AArch64ISD::ADRP,
llvm::AArch64ISD::ADR,
llvm::AArch64ISD::ADDlow,
llvm::AArch64ISD::LOADgot,
llvm::AArch64ISD::RET_FLAG,
llvm::AArch64ISD::BRCOND,
llvm::AArch64ISD::CSEL,
llvm::AArch64ISD::FCSEL,
llvm::AArch64ISD::CSINV,
llvm::AArch64ISD::CSNEG,
llvm::AArch64ISD::CSINC,
llvm::AArch64ISD::THREAD_POINTER,
llvm::AArch64ISD::ADC,
llvm::AArch64ISD::SBC,
llvm::AArch64ISD::ADDS,
llvm::AArch64ISD::SUBS,
llvm::AArch64ISD::ADCS,
llvm::AArch64ISD::SBCS,
llvm::AArch64ISD::ANDS,
llvm::AArch64ISD::CCMP,
llvm::AArch64ISD::CCMN,
llvm::AArch64ISD::FCCMP,
llvm::AArch64ISD::FCMP,
llvm::AArch64ISD::EXTR,
llvm::AArch64ISD::DUP,
llvm::AArch64ISD::DUPLANE8,
llvm::AArch64ISD::DUPLANE16,
llvm::AArch64ISD::DUPLANE32,
llvm::AArch64ISD::DUPLANE64,
llvm::AArch64ISD::MOVI,
llvm::AArch64ISD::MOVIshift,
llvm::AArch64ISD::MOVIedit,
llvm::AArch64ISD::MOVImsl,
llvm::AArch64ISD::FMOV,
llvm::AArch64ISD::MVNIshift,
llvm::AArch64ISD::MVNImsl,
llvm::AArch64ISD::BICi,
llvm::AArch64ISD::ORRi,
llvm::AArch64ISD::BSL,
llvm::AArch64ISD::NEG,
llvm::AArch64ISD::ZIP1,
llvm::AArch64ISD::ZIP2,
llvm::AArch64ISD::UZP1,
llvm::AArch64ISD::UZP2,
llvm::AArch64ISD::TRN1,
llvm::AArch64ISD::TRN2,
llvm::AArch64ISD::REV16,
llvm::AArch64ISD::REV32,
llvm::AArch64ISD::REV64,
llvm::AArch64ISD::EXT,
llvm::AArch64ISD::VSHL,
llvm::AArch64ISD::VLSHR,
llvm::AArch64ISD::VASHR,
llvm::AArch64ISD::SQSHL_I,
llvm::AArch64ISD::UQSHL_I,
llvm::AArch64ISD::SQSHLU_I,
llvm::AArch64ISD::SRSHR_I,
llvm::AArch64ISD::URSHR_I,
llvm::AArch64ISD::CMEQ,
llvm::AArch64ISD::CMGE,
llvm::AArch64ISD::CMGT,
llvm::AArch64ISD::CMHI,
llvm::AArch64ISD::CMHS,
llvm::AArch64ISD::FCMEQ,
llvm::AArch64ISD::FCMGE,
llvm::AArch64ISD::FCMGT,
llvm::AArch64ISD::CMEQz,
llvm::AArch64ISD::CMGEz,
llvm::AArch64ISD::CMGTz,
llvm::AArch64ISD::CMLEz,
llvm::AArch64ISD::CMLTz,
llvm::AArch64ISD::FCMEQz,
llvm::AArch64ISD::FCMGEz,
llvm::AArch64ISD::FCMGTz,
llvm::AArch64ISD::FCMLEz,
llvm::AArch64ISD::FCMLTz,
llvm::AArch64ISD::SADDV,
llvm::AArch64ISD::UADDV,
llvm::AArch64ISD::SMINV,
llvm::AArch64ISD::UMINV,
llvm::AArch64ISD::SMAXV,
llvm::AArch64ISD::UMAXV,
llvm::AArch64ISD::NOT,
llvm::AArch64ISD::BIT,
llvm::AArch64ISD::CBZ,
llvm::AArch64ISD::CBNZ,
llvm::AArch64ISD::TBZ,
llvm::AArch64ISD::TBNZ,
llvm::AArch64ISD::TC_RETURN,
llvm::AArch64ISD::PREFETCH,
llvm::AArch64ISD::SITOF,
llvm::AArch64ISD::UITOF,
llvm::AArch64ISD::NVCAST,
llvm::AArch64ISD::SMULL,
llvm::AArch64ISD::UMULL,
llvm::AArch64ISD::FRECPE,
llvm::AArch64ISD::FRECPS,
llvm::AArch64ISD::FRSQRTE,
llvm::AArch64ISD::FRSQRTS,
llvm::AArch64ISD::LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
llvm::AArch64ISD::LD3post,
llvm::AArch64ISD::LD4post,
llvm::AArch64ISD::ST2post,
llvm::AArch64ISD::ST3post,
llvm::AArch64ISD::ST4post,
llvm::AArch64ISD::LD1x2post,
llvm::AArch64ISD::LD1x3post,
llvm::AArch64ISD::LD1x4post,
llvm::AArch64ISD::ST1x2post,
llvm::AArch64ISD::ST1x3post,
llvm::AArch64ISD::ST1x4post,
llvm::AArch64ISD::LD1DUPpost,
llvm::AArch64ISD::LD2DUPpost,
llvm::AArch64ISD::LD3DUPpost,
llvm::AArch64ISD::LD4DUPpost,
llvm::AArch64ISD::LD1LANEpost,
llvm::AArch64ISD::LD2LANEpost,
llvm::AArch64ISD::LD3LANEpost,
llvm::AArch64ISD::LD4LANEpost,
llvm::AArch64ISD::ST2LANEpost,
llvm::AArch64ISD::ST3LANEpost,
llvm::AArch64ISD::ST4LANEpost
} |
