LLVM
8.0.1
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#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/BasicAliasAnalysis.h"
#include "llvm/Analysis/CFLAndersAliasAnalysis.h"
#include "llvm/Analysis/CFLSteensAliasAnalysis.h"
#include "llvm/Analysis/CallGraphSCCPass.h"
#include "llvm/Analysis/ScopedNoAliasAA.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/IR/IRPrintingPasses.h"
#include "llvm/IR/LegacyPassManager.h"
#include "llvm/IR/Verifier.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Threading.h"
#include "llvm/Support/SaveAndRestore.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils.h"
#include "llvm/Transforms/Utils/SymbolRewriter.h"
#include <cassert>
#include <string>
Go to the source code of this file.
Classes | |
struct | INITIALIZE_PASS::InsertedPass |
class | llvm::PassConfigImpl |
Namespaces | |
INITIALIZE_PASS | |
TargetPassConfig. | |
llvm | |
This class represents lattice values for constants. | |
Enumerations | |
enum | RunOutliner { AlwaysOutline, NeverOutline, TargetDefault } |
enum | CFLAAType { CFLAAType::None, CFLAAType::Steensgaard, CFLAAType::Andersen, CFLAAType::Both, CFLAAType::None, CFLAAType::Steensgaard, CFLAAType::Andersen, CFLAAType::Both } |
Functions | |
static IdentifyingPassPtr | applyDisable (IdentifyingPassPtr PassID, bool Override) |
Allow standard passes to be disabled by command line options. More... | |
static IdentifyingPassPtr | overridePass (AnalysisID StandardID, IdentifyingPassPtr TargetID) |
Allow standard passes to be disabled by the command line, regardless of who is adding the pass. More... | |
static const PassInfo * | getPassInfo (StringRef PassName) |
static AnalysisID | getPassIDFromName (StringRef PassName) |
static std::pair< StringRef, unsigned > | getPassNameAndInstanceNum (StringRef PassName) |
static FunctionPass * | useDefaultRegisterAllocator () |
-regalloc=... command line option. More... | |
static void | initializeDefaultRegisterAllocatorOnce () |
Variables | |
cl::opt< bool > | EnableIPRA ("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls.")) |
static cl::opt< bool > | DisablePostRASched ("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler")) |
static cl::opt< bool > | DisableBranchFold ("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding")) |
static cl::opt< bool > | DisableTailDuplicate ("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication")) |
static cl::opt< bool > | DisableEarlyTailDup ("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication")) |
static cl::opt< bool > | DisableBlockPlacement ("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement")) |
static cl::opt< bool > | EnableBlockPlacementStats ("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats")) |
static cl::opt< bool > | DisableSSC ("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring")) |
static cl::opt< bool > | DisableMachineDCE ("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination")) |
static cl::opt< bool > | DisableEarlyIfConversion ("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion")) |
static cl::opt< bool > | DisableMachineLICM ("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM")) |
static cl::opt< bool > | DisableMachineCSE ("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination")) |
static cl::opt< cl::boolOrDefault > | OptimizeRegAlloc ("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path.")) |
static cl::opt< bool > | DisablePostRAMachineLICM ("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM")) |
static cl::opt< bool > | DisableMachineSink ("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking")) |
static cl::opt< bool > | DisablePostRAMachineSink ("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking")) |
static cl::opt< bool > | DisableLSR ("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass")) |
static cl::opt< bool > | DisableConstantHoisting ("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting")) |
static cl::opt< bool > | DisableCGP ("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare")) |
static cl::opt< bool > | DisableCopyProp ("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass")) |
static cl::opt< bool > | DisablePartialLibcallInlining ("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining")) |
static cl::opt< bool > | EnableImplicitNullChecks ("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden) |
static cl::opt< bool > | DisableMergeICmps ("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden) |
static cl::opt< bool > | PrintLSR ("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass")) |
static cl::opt< bool > | PrintISelInput ("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass")) |
static cl::opt< bool > | PrintGCInfo ("print-gc", cl::Hidden, cl::desc("Dump garbage collector data")) |
static cl::opt< cl::boolOrDefault > | VerifyMachineCode ("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::ZeroOrMore) |
static cl::opt< RunOutliner > | EnableMachineOutliner ("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(TargetDefault), cl::values(clEnumValN(AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(NeverOutline, "never", "Disable all outlining"), clEnumValN(AlwaysOutline, "", ""))) |
static cl::opt< cl::boolOrDefault > | EnableFastISelOption ("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector")) |
static cl::opt< cl::boolOrDefault > | EnableGlobalISelOption ("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector")) |
static cl::opt< std::string > | PrintMachineInstrs ("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden) |
static cl::opt< GlobalISelAbortMode > | EnableGlobalISelAbort ("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure"))) |
cl::opt< bool > | MISchedPostRA ("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")) |
static cl::opt< bool > | EarlyLiveIntervals ("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline")) |
static cl::opt< CFLAAType > | UseCFLAA ("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA"))) |
const char * | StartAfterOptName = "start-after" |
Option names for limiting the codegen pipeline. More... | |
const char * | StartBeforeOptName = "start-before" |
const char * | StopAfterOptName = "stop-after" |
const char * | StopBeforeOptName = "stop-before" |
static cl::opt< std::string > | StartAfterOpt (StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden) |
static cl::opt< std::string > | StartBeforeOpt (StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden) |
static cl::opt< std::string > | StopAfterOpt (StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden) |
static cl::opt< std::string > | StopBeforeOpt (StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden) |
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > | RegAlloc ("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use")) |
static llvm::once_flag | InitializeDefaultRegisterAllocatorFlag |
A dummy default pass factory indicates whether the register allocator is overridden on the command line. More... | |
static RegisterRegAlloc | defaultRegAlloc ("default", "pick register allocator based on -O option", useDefaultRegisterAllocator) |
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Enumerator | |
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None | |
Steensgaard | |
Andersen | |
Both | |
None | |
Steensgaard | |
Andersen | |
Both |
Definition at line 163 of file TargetPassConfig.cpp.
enum RunOutliner |
Enumerator | |
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AlwaysOutline | |
NeverOutline | |
TargetDefault |
Definition at line 115 of file TargetPassConfig.cpp.
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Allow standard passes to be disabled by command line options.
This supports simple binary flags that either suppress the pass or do nothing. i.e. -disable-mypass=false has no effect. These should be converted to boolOrDefault in order to use applyOverride.
Definition at line 207 of file TargetPassConfig.cpp.
Referenced by overridePass().
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Definition at line 343 of file TargetPassConfig.cpp.
References getPassInfo(), and llvm::PassInfo::getTypeInfo().
Referenced by getPassNameAndInstanceNum().
Definition at line 331 of file TargetPassConfig.cpp.
References llvm::StringRef::empty(), llvm::PassRegistry::getPassInfo(), llvm::PassRegistry::getPassRegistry(), and llvm::report_fatal_error().
Referenced by llvm::TargetPassConfig::addMachinePasses(), llvm::PMTopLevelManager::findAnalysisPassInfo(), and getPassIDFromName().
Definition at line 349 of file TargetPassConfig.cpp.
References llvm::StringRef::empty(), llvm::StringRef::getAsInteger(), getPassIDFromName(), Name, llvm::report_fatal_error(), llvm::StringRef::split(), StartAfterOpt, StartBeforeOpt, StopAfterOpt, and StopBeforeOpt.
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Definition at line 1055 of file TargetPassConfig.cpp.
References llvm::RegisterRegAlloc::getDefault(), RegAlloc, and llvm::RegisterRegAlloc::setDefault().
Referenced by llvm::TargetPassConfig::createRegAllocPass().
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Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
StandardID is the pass identified in the standard pass pipeline and provided to addPass(). It may be a target-specific ID in the case that the target directly adds its own pass, but in that case we harmlessly fall through.
TargetID is the pass that the target has configured to override StandardID.
StandardID may be a pseudo ID. In that case TargetID is the name of the real pass to run. This allows multiple options to control a single pass depending on where in the pipeline that pass is added.
Definition at line 226 of file TargetPassConfig.cpp.
References applyDisable(), llvm::BranchFolderPassID, llvm::DeadMachineInstructionElimID, DisableBlockPlacement, DisableBranchFold, DisableCopyProp, DisableEarlyIfConversion, DisableEarlyTailDup, DisableMachineCSE, DisableMachineDCE, DisableMachineLICM, DisableMachineSink, DisablePostRAMachineLICM, DisablePostRAMachineSink, DisablePostRASched, DisableSSC, DisableTailDuplicate, llvm::EarlyIfConverterID, llvm::EarlyMachineLICMID, llvm::EarlyTailDuplicateID, llvm::TargetPassConfig::ID, INITIALIZE_PASS, llvm::MachineBlockPlacementID, llvm::MachineCopyPropagationID, llvm::MachineCSEID, llvm::MachineLICMID, llvm::MachineSinkingID, llvm::PostRAMachineSinkingID, llvm::PostRASchedulerID, llvm::StackSlotColoringID, and llvm::TailDuplicateID.
Referenced by llvm::TargetPassConfig::addPass(), and llvm::TargetPassConfig::isPassSubstitutedOrOverridden().
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-regalloc=... command line option.
Definition at line 836 of file TargetPassConfig.cpp.
References llvm::cl::Hidden, llvm::cl::init(), and RegAlloc.
Referenced by llvm::TargetPassConfig::addMachinePasses(), and llvm::TargetPassConfig::createRegAllocPass().
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Referenced by overridePass().
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Referenced by overridePass().
Referenced by llvm::TargetPassConfig::addCodeGenPrepare().
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Referenced by llvm::TargetPassConfig::addIRPasses().
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Referenced by overridePass().
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Referenced by overridePass().
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Referenced by overridePass().
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Referenced by llvm::TargetPassConfig::addIRPasses().
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Referenced by overridePass().
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Referenced by overridePass().
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Referenced by overridePass().
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Referenced by overridePass().
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Referenced by llvm::TargetPassConfig::addIRPasses().
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Referenced by llvm::TargetPassConfig::addIRPasses().
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Referenced by overridePass().
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Referenced by overridePass().
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Referenced by overridePass().
Referenced by overridePass().
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Referenced by overridePass().
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Referenced by llvm::TargetPassConfig::addBlockPlacement().
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Referenced by llvm::TargetPassConfig::addMachinePasses().
cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls.")) |
Referenced by llvm::TargetPassConfig::TargetPassConfig().
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A dummy default pass factory indicates whether the register allocator is overridden on the command line.
Definition at line 1048 of file TargetPassConfig.cpp.
cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")) |
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Referenced by llvm::TargetPassConfig::getOptimizeRegAlloc().
Referenced by llvm::TargetPassConfig::addMachinePasses().
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Referenced by llvm::TargetPassConfig::addISelPrepare().
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Referenced by llvm::TargetPassConfig::addIRPasses().
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Referenced by initializeDefaultRegisterAllocatorOnce(), and useDefaultRegisterAllocator().
Option names for limiting the codegen pipeline.
Those are used in error reporting and we didn't want to duplicate their names all over the place.
Definition at line 178 of file TargetPassConfig.cpp.
Referenced by llvm::TargetPassConfig::getLimitedCodeGenPipelineReason().
Definition at line 179 of file TargetPassConfig.cpp.
Referenced by llvm::TargetPassConfig::getLimitedCodeGenPipelineReason().
Definition at line 180 of file TargetPassConfig.cpp.
Referenced by llvm::TargetPassConfig::getLimitedCodeGenPipelineReason().
Definition at line 181 of file TargetPassConfig.cpp.
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Referenced by llvm::TargetPassConfig::addVerifyPass().