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| cl::opt< bool > | llvm::ForceTopDown ("misched-topdown", cl::Hidden, cl::desc("Force top-down list scheduling")) |
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| cl::opt< bool > | llvm::ForceBottomUp ("misched-bottomup", cl::Hidden, cl::desc("Force bottom-up list scheduling")) |
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| | INITIALIZE_PASS_BEGIN (MachineScheduler, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(MachineScheduler |
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| | INITIALIZE_PASS (PostMachineScheduler, "postmisched", "PostRA Machine Instruction Scheduler", false, false) PostMachineScheduler |
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| static ScheduleDAGInstrs * | useDefaultMachineSched (MachineSchedContext *C) |
| | A dummy default scheduler factory indicates whether the scheduler is overridden on the command line. More...
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| static MachineBasicBlock::const_iterator | priorNonDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator Beg) |
| | Decrement this iterator until reaching the top or a non-debug instr. More...
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| static MachineBasicBlock::iterator | priorNonDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator Beg) |
| | Non-const version. More...
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| static MachineBasicBlock::const_iterator | nextIfDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator End) |
| | If this iterator is a debug value, increment until reaching the End or a non-debug instruction. More...
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| static MachineBasicBlock::iterator | nextIfDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End) |
| | Non-const version. More...
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| static bool | isSchedBoundary (MachineBasicBlock::iterator MI, MachineBasicBlock *MBB, MachineFunction *MF, const TargetInstrInfo *TII) |
| | Return true of the given instruction should not be included in a scheduling region. More...
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| static void | getSchedRegions (MachineBasicBlock *MBB, MBBRegionsVector &Regions, bool RegionsTopDown) |
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| std::unique_ptr< ScheduleDAGMutation > | llvm::createLoadClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) |
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| std::unique_ptr< ScheduleDAGMutation > | llvm::createStoreClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) |
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| std::unique_ptr< ScheduleDAGMutation > | llvm::createCopyConstrainDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) |
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| static bool | checkResourceLimit (unsigned LFactor, unsigned Count, unsigned Latency) |
| | Given a Count of resource usage and a Latency value, return true if a SchedBoundary becomes resource limited. More...
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| static unsigned | computeRemLatency (SchedBoundary &CurrZone) |
| | Compute remaining latency. More...
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| bool | llvm::tryLess (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) |
| | Return true if this heuristic determines order. More...
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| bool | llvm::tryGreater (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) |
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| bool | llvm::tryLatency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone) |
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| static void | tracePick (GenericSchedulerBase::CandReason Reason, bool IsTop) |
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| static void | tracePick (const GenericSchedulerBase::SchedCandidate &Cand) |
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| bool | llvm::tryPressure (const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF) |
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| unsigned | llvm::getWeakLeft (const SUnit *SU, bool isTop) |
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| int | llvm::biasPhysReg (const SUnit *SU, bool isTop) |
| | Minimize physical register live ranges. More...
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| |
| static ScheduleDAGInstrs * | createConveringSched (MachineSchedContext *C) |
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| static ScheduleDAGInstrs * | createILPMaxScheduler (MachineSchedContext *C) |
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| static ScheduleDAGInstrs * | createILPMinScheduler (MachineSchedContext *C) |
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| static ScheduleDAGInstrs * | createInstructionShuffler (MachineSchedContext *C) |
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| cl::opt< bool > | llvm::DumpCriticalPathLength ("misched-dcpl", cl::Hidden, cl::desc("Print critical path length to stdout")) |
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| static cl::opt< bool > | ViewMISchedDAGs ("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed")) |
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| static cl::opt< unsigned > | ViewMISchedCutoff ("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff")) |
| | In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them. More...
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| static cl::opt< unsigned > | MISchedCutoff ("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U)) |
| |
| static cl::opt< std::string > | SchedOnlyFunc ("misched-only-func", cl::Hidden, cl::desc("Only schedule this function")) |
| |
| static cl::opt< unsigned > | SchedOnlyBlock ("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#")) |
| |
| static cl::opt< bool > | PrintDAGs ("misched-print-dags", cl::Hidden, cl::desc("Print schedule DAGs")) |
| |
| static cl::opt< unsigned > | ReadyListLimit ("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256)) |
| | Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists. More...
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| |
| static cl::opt< bool > | EnableRegPressure ("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true)) |
| |
| static cl::opt< bool > | EnableCyclicPath ("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true)) |
| |
| static cl::opt< bool > | EnableMemOpCluster ("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true)) |
| |
| static cl::opt< bool > | VerifyScheduling ("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling")) |
| |
| static const unsigned | MinSubtreeSize = 8 |
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| | DEBUG_TYPE |
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| Machine Instruction | Scheduler |
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| Machine Instruction | false |
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| static cl::opt< MachineSchedRegistry::ScheduleDAGCtor, false, RegisterPassParser< MachineSchedRegistry > > | MachineSchedOpt ("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use")) |
| | MachineSchedOpt allows command line selection of the scheduler. More...
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| static MachineSchedRegistry | DefaultSchedRegistry ("default", "Use the target's default scheduler choice.", useDefaultMachineSched) |
| |
| static cl::opt< bool > | EnableMachineSched ("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden) |
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| static cl::opt< bool > | EnablePostRAMachineSched ("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden) |
| |
| static const unsigned | InvalidCycle = ~0U |
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| static MachineSchedRegistry | GenericSchedRegistry ("converge", "Standard converging scheduler.", createConveringSched) |
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| static MachineSchedRegistry | ILPMaxRegistry ("ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler) |
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| static MachineSchedRegistry | ILPMinRegistry ("ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler) |
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| static MachineSchedRegistry | ShufflerRegistry ("shuffle", "Shuffle machine instructions alternating directions", createInstructionShuffler) |
| |
Return true of the given instruction should not be included in a scheduling region.
MachineScheduler does not currently support scheduling across calls. To handle calls, the DAG builder needs to be modified to create register anti/output dependencies on the registers clobbered by the call's regmask operand. In PreRA scheduling, the stack pointer adjustment already prevents scheduling across calls. In PostRA scheduling, we need the isCall to enforce the boundary, but there would be no benefit to postRA scheduling across calls this late anyway.
Definition at line 438 of file MachineScheduler.cpp.
References B, E, llvm::TargetInstrInfo::isSchedulingBoundary(), and N.
Referenced by getSchedRegions().
