#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/PriorityQueue.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/CodeGen/ScheduleDFS.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <string>
#include <tuple>
#include <utility>
#include <vector>

Classes
struct	llvm::GraphTraits< ScheduleDAGMI * >

struct	llvm::DOTGraphTraits< ScheduleDAGMI * >

Namespaces
	llvm
	This class represents lattice values for constants.

Macros
#define	DEBUG_TYPE "machine-scheduler"

Typedefs
using	MBBRegionsVector = SmallVector< SchedRegion, 16 >

Functions
cl::opt< bool >	llvm::ForceTopDown ("misched-topdown", cl::Hidden, cl::desc("Force top-down list scheduling"))

cl::opt< bool >	llvm::ForceBottomUp ("misched-bottomup", cl::Hidden, cl::desc("Force bottom-up list scheduling"))

	INITIALIZE_PASS_BEGIN (MachineScheduler, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(MachineScheduler

	INITIALIZE_PASS (PostMachineScheduler, "postmisched", "PostRA Machine Instruction Scheduler", false, false) PostMachineScheduler

static ScheduleDAGInstrs *	useDefaultMachineSched (MachineSchedContext *C)
	A dummy default scheduler factory indicates whether the scheduler is overridden on the command line. More...

static MachineBasicBlock::const_iterator	priorNonDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator Beg)
	Decrement this iterator until reaching the top or a non-debug instr. More...

static MachineBasicBlock::iterator	priorNonDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator Beg)
	Non-const version. More...

static MachineBasicBlock::const_iterator	nextIfDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator End)
	If this iterator is a debug value, increment until reaching the End or a non-debug instruction. More...

static MachineBasicBlock::iterator	nextIfDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End)
	Non-const version. More...

static bool	isSchedBoundary (MachineBasicBlock::iterator MI, MachineBasicBlock MBB, MachineFunction MF, const TargetInstrInfo *TII)
	Return true of the given instruction should not be included in a scheduling region. More...

static void	getSchedRegions (MachineBasicBlock *MBB, MBBRegionsVector &Regions, bool RegionsTopDown)

std::unique_ptr< ScheduleDAGMutation >	llvm::createLoadClusterDAGMutation (const TargetInstrInfo TII, const TargetRegisterInfo TRI)

std::unique_ptr< ScheduleDAGMutation >	llvm::createStoreClusterDAGMutation (const TargetInstrInfo TII, const TargetRegisterInfo TRI)

std::unique_ptr< ScheduleDAGMutation >	llvm::createCopyConstrainDAGMutation (const TargetInstrInfo TII, const TargetRegisterInfo TRI)

static bool	checkResourceLimit (unsigned LFactor, unsigned Count, unsigned Latency)
	Given a Count of resource usage and a Latency value, return true if a SchedBoundary becomes resource limited. More...

static unsigned	computeRemLatency (SchedBoundary &CurrZone)
	Compute remaining latency. More...

bool	llvm::tryLess (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
	Return true if this heuristic determines order. More...

bool	llvm::tryGreater (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)

bool	llvm::tryLatency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)

static void	tracePick (GenericSchedulerBase::CandReason Reason, bool IsTop)

static void	tracePick (const GenericSchedulerBase::SchedCandidate &Cand)

bool	llvm::tryPressure (const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)

unsigned	llvm::getWeakLeft (const SUnit *SU, bool isTop)

int	llvm::biasPhysReg (const SUnit *SU, bool isTop)
	Minimize physical register live ranges. More...

static ScheduleDAGInstrs *	createConveringSched (MachineSchedContext *C)

static ScheduleDAGInstrs *	createILPMaxScheduler (MachineSchedContext *C)

static ScheduleDAGInstrs *	createILPMinScheduler (MachineSchedContext *C)

static ScheduleDAGInstrs *	createInstructionShuffler (MachineSchedContext *C)

Variables
cl::opt< bool >	llvm::DumpCriticalPathLength ("misched-dcpl", cl::Hidden, cl::desc("Print critical path length to stdout"))

static cl::opt< bool >	ViewMISchedDAGs ("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed"))

static cl::opt< unsigned >	ViewMISchedCutoff ("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff"))
	In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them. More...

static cl::opt< unsigned >	MISchedCutoff ("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U))

static cl::opt< std::string >	SchedOnlyFunc ("misched-only-func", cl::Hidden, cl::desc("Only schedule this function"))

static cl::opt< unsigned >	SchedOnlyBlock ("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#"))

static cl::opt< bool >	PrintDAGs ("misched-print-dags", cl::Hidden, cl::desc("Print schedule DAGs"))

static cl::opt< unsigned >	ReadyListLimit ("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256))
	Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists. More...

static cl::opt< bool >	EnableRegPressure ("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true))

static cl::opt< bool >	EnableCyclicPath ("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true))

static cl::opt< bool >	EnableMemOpCluster ("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true))

static cl::opt< bool >	VerifyScheduling ("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling"))

static const unsigned	MinSubtreeSize = 8

	DEBUG_TYPE

Machine Instruction	Scheduler

Machine Instruction	false

static cl::opt< MachineSchedRegistry::ScheduleDAGCtor, false, RegisterPassParser< MachineSchedRegistry > >	MachineSchedOpt ("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use"))
	MachineSchedOpt allows command line selection of the scheduler. More...

static MachineSchedRegistry	DefaultSchedRegistry ("default", "Use the target's default scheduler choice.", useDefaultMachineSched)

static cl::opt< bool >	EnableMachineSched ("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden)

static cl::opt< bool >	EnablePostRAMachineSched ("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden)

static const unsigned	InvalidCycle = ~0U

static MachineSchedRegistry	GenericSchedRegistry ("converge", "Standard converging scheduler.", createConveringSched)

static MachineSchedRegistry	ILPMaxRegistry ("ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler)

static MachineSchedRegistry	ILPMinRegistry ("ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler)

static MachineSchedRegistry	ShufflerRegistry ("shuffle", "Shuffle machine instructions alternating directions", createInstructionShuffler)

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "machine-scheduler"

Definition at line 74 of file MachineScheduler.cpp.

Typedef Documentation

◆ MBBRegionsVector

using MBBRegionsVector = SmallVector<SchedRegion, 16>

Definition at line 463 of file MachineScheduler.cpp.

Function Documentation

◆ checkResourceLimit()

static bool checkResourceLimit	(	unsigned	LFactor,
		unsigned	Count,
		unsigned	Latency
	)

static

Given a Count of resource usage and a Latency value, return true if a SchedBoundary becomes resource limited.

Definition at line 1860 of file MachineScheduler.cpp.

Referenced by llvm::SchedBoundary::bumpCycle(), llvm::SchedBoundary::bumpNode(), and llvm::GenericSchedulerBase::setPolicy().

◆ computeRemLatency()

static unsigned computeRemLatency ( SchedBoundary & CurrZone )

static

Compute remaining latency.

We need this both to determine whether the overall schedule has become latency-limited and whether the instructions outside this zone are resource or latency limited.

The "dependent" latency is updated incrementally during scheduling as the max height/depth of scheduled nodes minus the cycles since it was scheduled: DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone

The "independent" latency is the max ready queue depth: ILat = max N.depth for N in Available|Pending

RemainingLatency is the greater of independent and dependent latency.

These computations are expensive, especially in DAGs with many edges, so only do them if necessary.

Definition at line 2453 of file MachineScheduler.cpp.

References llvm::SchedBoundary::Available, llvm::ReadyQueue::elements(), llvm::SchedBoundary::findMaxLatency(), llvm::SchedBoundary::getCurrCycle(), llvm::SchedBoundary::getDependentLatency(), llvm::max(), and llvm::SchedBoundary::Pending.

Referenced by llvm::GenericSchedulerBase::setPolicy().

◆ createConveringSched()

static ScheduleDAGInstrs* createConveringSched ( MachineSchedContext * C )

static

Definition at line 3283 of file MachineScheduler.cpp.

References llvm::createGenericSchedLive(), and GenericSchedRegistry.

◆ createILPMaxScheduler()

static ScheduleDAGInstrs* createILPMaxScheduler ( MachineSchedContext * C )

static

Definition at line 3535 of file MachineScheduler.cpp.

Referenced by createILPMinScheduler().

◆ createILPMinScheduler()

static ScheduleDAGInstrs* createILPMinScheduler ( MachineSchedContext * C )

static

Definition at line 3538 of file MachineScheduler.cpp.

References B, llvm::PriorityQueue< T, Sequence, Compare >::clear(), createILPMaxScheduler(), ILPMaxRegistry, ILPMinRegistry, llvm::MachineSchedStrategy::initialize(), llvm::SUnit::isScheduled, llvm::SUnit::NodeNum, llvm::MachineSchedStrategy::pickNode(), llvm::MachineSchedStrategy::releaseBottomNode(), llvm::MachineSchedStrategy::releaseTopNode(), and llvm::MachineSchedStrategy::schedNode().

◆ createInstructionShuffler()

static ScheduleDAGInstrs* createInstructionShuffler ( MachineSchedContext * C )

static

Definition at line 3627 of file MachineScheduler.cpp.

References assert(), llvm::ForceBottomUp, llvm::ForceTopDown, and ShufflerRegistry.

◆ getSchedRegions()

static void getSchedRegions	(	MachineBasicBlock *	MBB,
		MBBRegionsVector &	Regions,
		bool	RegionsTopDown
	)

static

Definition at line 466 of file MachineScheduler.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MachineBasicBlock::begin(), llvm::dbgs(), llvm::ScheduleDAGInstrs::doMBBSchedRegionsTopDown(), llvm::DumpCriticalPathLength, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAGInstrs::enterRegion(), llvm::errs(), llvm::ScheduleDAGInstrs::exitRegion(), llvm::ScheduleDAGInstrs::finalizeSchedule(), llvm::ScheduleDAGInstrs::finishBlock(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::cl::Option::getNumOccurrences(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineInstr::isDebugInstr(), isSchedBoundary(), LLVM_DEBUG, MI, llvm::RISCVFenceField::O, print(), llvm::printMBBReference(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::reverse(), llvm::ScheduleDAGInstrs::schedule(), Scheduler, llvm::ScheduleDAGInstrs::startBlock(), and TII.

◆ INITIALIZE_PASS()

INITIALIZE_PASS	(	PostMachineScheduler	,
		"postmisched"	,
		"PostRA Machine Instruction Scheduler"	,
		false	,
		false
	)

Definition at line 229 of file MachineScheduler.cpp.

References llvm::AnalysisUsage::addRequired(), llvm::AnalysisUsage::addRequiredID(), llvm::MachineFunctionPass::getAnalysisUsage(), llvm::PassRegistry::getPassRegistry(), llvm::initializePostMachineSchedulerPass(), llvm::MachineDominatorsID, llvm::MachineSchedRegistry::Registry, and llvm::AnalysisUsage::setPreservesCFG().

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	MachineScheduler	,
		DEBUG_TYPE	,
		"Machine Instruction Scheduler"	,
		false	,
		false
	)

◆ isSchedBoundary()

static bool isSchedBoundary	(	MachineBasicBlock::iterator	MI,
		MachineBasicBlock *	MBB,
		MachineFunction *	MF,
		const TargetInstrInfo *	TII
	)

static

Return true of the given instruction should not be included in a scheduling region.

MachineScheduler does not currently support scheduling across calls. To handle calls, the DAG builder needs to be modified to create register anti/output dependencies on the registers clobbered by the call's regmask operand. In PreRA scheduling, the stack pointer adjustment already prevents scheduling across calls. In PostRA scheduling, we need the isCall to enforce the boundary, but there would be no benefit to postRA scheduling across calls this late anyway.

Definition at line 438 of file MachineScheduler.cpp.

References B, E, llvm::TargetInstrInfo::isSchedulingBoundary(), and N.

Referenced by getSchedRegions().

◆ nextIfDebug() [1/2]

static MachineBasicBlock::const_iterator nextIfDebug	(	MachineBasicBlock::const_iterator	I,
		MachineBasicBlock::const_iterator	End
	)

static

If this iterator is a debug value, increment until reaching the End or a non-debug instruction.

Definition at line 297 of file MachineScheduler.cpp.

Referenced by llvm::createCopyConstrainDAGMutation(), llvm::ScheduleDAGMI::initQueues(), llvm::ScheduleDAGMI::schedule(), llvm::ScheduleDAGMILive::scheduleMI(), and llvm::ScheduleDAGMILive::updatePressureDiffs().

◆ nextIfDebug() [2/2]

static MachineBasicBlock::iterator nextIfDebug	(	MachineBasicBlock::iterator	I,
		MachineBasicBlock::const_iterator	End
	)

static

Non-const version.

Definition at line 308 of file MachineScheduler.cpp.

◆ priorNonDebug() [1/2]

static MachineBasicBlock::const_iterator priorNonDebug	(	MachineBasicBlock::const_iterator	I,
		MachineBasicBlock::const_iterator	Beg
	)

static

Decrement this iterator until reaching the top or a non-debug instr.

Definition at line 276 of file MachineScheduler.cpp.

References assert(), and I.

Referenced by llvm::createCopyConstrainDAGMutation(), llvm::ScheduleDAGMILive::initRegPressure(), priorNonDebug(), llvm::ScheduleDAGMI::schedule(), and llvm::ScheduleDAGMILive::scheduleMI().

◆ priorNonDebug() [2/2]

static MachineBasicBlock::iterator priorNonDebug	(	MachineBasicBlock::iterator	I,
		MachineBasicBlock::const_iterator	Beg
	)

static

Non-const version.

Definition at line 288 of file MachineScheduler.cpp.

References llvm::MachineInstrBundleIterator< Ty, IsReverse >::getNonConstIterator(), and priorNonDebug().

◆ tracePick() [1/2]

static void tracePick	(	GenericSchedulerBase::CandReason	Reason,
		bool	IsTop
	)

static

Definition at line 2677 of file MachineScheduler.cpp.

References llvm::dbgs(), llvm::GenericSchedulerBase::getReasonStr(), and LLVM_DEBUG.

Referenced by llvm::GenericScheduler::pickNode(), llvm::PostGenericScheduler::pickNode(), llvm::GenericScheduler::pickNodeBidirectional(), and tracePick().

◆ tracePick() [2/2]

static void tracePick ( const GenericSchedulerBase::SchedCandidate & Cand )

static

Definition at line 2682 of file MachineScheduler.cpp.

References llvm::GenericSchedulerBase::SchedCandidate::AtTop, llvm::GenericSchedulerBase::SchedCandidate::Reason, and tracePick().

◆ useDefaultMachineSched()

static ScheduleDAGInstrs* useDefaultMachineSched ( MachineSchedContext * C )

static

A dummy default scheduler factory indicates whether the scheduler is overridden on the command line.

Definition at line 249 of file MachineScheduler.cpp.

References DefaultSchedRegistry, EnableMachineSched, EnablePostRAMachineSched, llvm::cl::Hidden, llvm::cl::init(), and MachineSchedOpt.

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 205 of file MachineScheduler.cpp.

◆ DefaultSchedRegistry

MachineSchedRegistry DefaultSchedRegistry("default", "Use the target's default scheduler choice.", useDefaultMachineSched)

static

Referenced by useDefaultMachineSched().

◆ EnableCyclicPath

cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true))

static

◆ EnableMachineSched

cl::opt<bool> EnableMachineSched("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden)

static

Referenced by useDefaultMachineSched().

◆ EnableMemOpCluster

cl::opt<bool> EnableMemOpCluster("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true))

static

◆ EnablePostRAMachineSched

cl::opt<bool> EnablePostRAMachineSched("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden)

static

Referenced by useDefaultMachineSched().

◆ EnableRegPressure

cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true))

static

◆ false

Machine Instruction false

Definition at line 205 of file MachineScheduler.cpp.

◆ GenericSchedRegistry

MachineSchedRegistry GenericSchedRegistry("converge", "Standard converging scheduler.", createConveringSched)

static

Referenced by createConveringSched().

◆ ILPMaxRegistry

MachineSchedRegistry ILPMaxRegistry("ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler)

static

Referenced by createILPMinScheduler().

◆ ILPMinRegistry

MachineSchedRegistry ILPMinRegistry("ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler)

static

Referenced by createILPMinScheduler().

◆ InvalidCycle

const unsigned InvalidCycle = ~0U

static

Definition at line 1854 of file MachineScheduler.cpp.

Referenced by llvm::SchedBoundary::init().

◆ MachineSchedOpt

cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false, RegisterPassParser<MachineSchedRegistry> > MachineSchedOpt("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use"))

static

MachineSchedOpt allows command line selection of the scheduler.

Referenced by useDefaultMachineSched().

◆ MinSubtreeSize

const unsigned MinSubtreeSize = 8

static

Definition at line 130 of file MachineScheduler.cpp.

◆ MISchedCutoff

cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U))

static

◆ PrintDAGs

cl::opt<bool> PrintDAGs("misched-print-dags", cl::Hidden, cl::desc("Print schedule DAGs"))

static

◆ ReadyListLimit

cl::opt<unsigned> ReadyListLimit("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256))

static

Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists.

Referenced by llvm::SchedBoundary::releaseNode(), and llvm::SchedBoundary::releasePending().

◆ SchedOnlyBlock

cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#"))

static

◆ SchedOnlyFunc

cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden, cl::desc("Only schedule this function"))

static

◆ Scheduler

Machine Instruction Scheduler

Definition at line 205 of file MachineScheduler.cpp.

Referenced by llvm::TaskQueue::async(), getSchedRegions(), INITIALIZE_PASS(), llvm::SIScheduleDAGMI::schedule(), llvm::SIScheduler::scheduleVariant(), llvm::MachineSchedContext::~MachineSchedContext(), and llvm::TaskQueue::~TaskQueue().

◆ ShufflerRegistry

MachineSchedRegistry ShufflerRegistry("shuffle", "Shuffle machine instructions alternating directions", createInstructionShuffler)

static

Referenced by createInstructionShuffler().

◆ VerifyScheduling

cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling"))

static

◆ ViewMISchedCutoff

cl::opt<unsigned> ViewMISchedCutoff("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff"))

static

In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them.

◆ ViewMISchedDAGs

cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed"))

static

Classes

Namespaces

Macros

Typedefs

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Typedef Documentation

◆ MBBRegionsVector

Function Documentation

◆ checkResourceLimit()

◆ computeRemLatency()

◆ createConveringSched()

◆ createILPMaxScheduler()

◆ createILPMinScheduler()

◆ createInstructionShuffler()

◆ getSchedRegions()

◆ INITIALIZE_PASS()

◆ INITIALIZE_PASS_BEGIN()

◆ isSchedBoundary()

◆ nextIfDebug() [1/2]

◆ nextIfDebug() [2/2]

◆ priorNonDebug() [1/2]

◆ priorNonDebug() [2/2]

◆ tracePick() [1/2]

◆ tracePick() [2/2]

◆ useDefaultMachineSched()

Variable Documentation

◆ DEBUG_TYPE

◆ DefaultSchedRegistry

◆ EnableCyclicPath

◆ EnableMachineSched

◆ EnableMemOpCluster

◆ EnablePostRAMachineSched

◆ EnableRegPressure

◆ false

◆ GenericSchedRegistry

◆ ILPMaxRegistry

◆ ILPMinRegistry

◆ InvalidCycle

◆ MachineSchedOpt

◆ MinSubtreeSize

◆ MISchedCutoff

◆ PrintDAGs

◆ ReadyListLimit

◆ SchedOnlyBlock

◆ SchedOnlyFunc

◆ Scheduler

◆ ShufflerRegistry

◆ VerifyScheduling

◆ ViewMISchedCutoff

◆ ViewMISchedDAGs