#include "PPCISelLowering.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCCCState.h"
#include "PPCCallingConv.h"
#include "PPCFrameLowering.h"
#include "PPCInstrInfo.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCPerfectShuffle.h"
#include "PPCRegisterInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/None.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallSite.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Use.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <list>
#include <utility>
#include <vector>
#include "PPCGenCallingConv.inc"

Macros
#define	DEBUG_TYPE "ppc-lowering"

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")

	STATISTIC (NumSiblingCalls, "Number of sibling calls")

static bool	isNByteElemShuffleMask (ShuffleVectorSDNode *N, unsigned Width, int StepLen)
	Check that the mask is shuffling N byte elements. More...

static void	getMaxByValAlign (Type *Ty, unsigned &MaxAlign, unsigned MaxMaxAlign)
	getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment. More...

static bool	isFloatingPointZero (SDValue Op)
	isFloatingPointZero - Return true if this is 0.0 or -0.0. More...

static bool	isConstantOrUndef (int Op, int Val)
	isConstantOrUndef - Op is either an undef node or a ConstantSDNode. More...

static bool	isVMerge (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart)
	isVMerge - Common function, used to match vmrg* shuffles. More...

static bool	isVMerge (ShuffleVectorSDNode *N, unsigned IndexOffset, unsigned RHSStartValue)
	Common function used to match vmrgew and vmrgow shuffles. More...

static bool	isXXBRShuffleMaskHelper (ShuffleVectorSDNode *N, int Width)

static void	fixupFuncForFI (SelectionDAG &DAG, int FrameIdx, EVT VT)

static bool	usePartialVectorLoads (SDNode *N)
	Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence. More...

static void	getLabelAccessInfo (bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
	Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. More...

static SDValue	LowerLabelRef (SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)

static void	setUsesTOCBasePtr (MachineFunction &MF)

static void	setUsesTOCBasePtr (SelectionDAG &DAG)

static SDValue	getTOCEntry (SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit, SDValue GA)

static unsigned	CalculateStackSlotSize (EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
	CalculateStackSlotSize - Calculates the size reserved for this argument on the stack. More...

static unsigned	CalculateStackSlotAlignment (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
	CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack. More...

static bool	CalculateStackSlotUsed (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs, bool HasQPX)
	CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers). More...

static unsigned	EnsureStackAlignment (const PPCFrameLowering *Lowering, unsigned NumBytes)
	EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target. More...

static int	CalculateTailCallSPDiff (SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
	CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall. More...

static bool	isFunctionGlobalAddress (SDValue Callee)

static bool	callsShareTOCBase (const Function *Caller, SDValue Callee, const TargetMachine &TM)

static bool	needStackSlotPassParameters (const PPCSubtarget &Subtarget, const SmallVectorImpl< ISD::OutputArg > &Outs)

static bool	hasSameArgumentList (const Function *CallerFn, ImmutableCallSite CS)

static bool	areCallingConvEligibleForTCO_64SVR4 (CallingConv::ID CallerCC, CallingConv::ID CalleeCC)

static SDNode *	isBLACompatibleAddress (SDValue Op, SelectionDAG &DAG)
	isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction. More...

static void	StoreTailCallArgumentsToStackSlot (SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, const SDLoc &dl)
	StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. More...

static SDValue	EmitTailCallStoreFPAndRetAddr (SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl)
	EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call. More...

static void	CalculateTailCallArgDest (SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
	CalculateTailCallArgDest - Remember Argument for later processing. More...

static SDValue	CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
	CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size". More...

static void	LowerMemOpCallTo (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
	LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls. More...

static void	PrepareTailCall (SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)

static unsigned	PrepareCall (SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDValue CallSeqStart, const SDLoc &dl, int SPDiff, bool isTailCall, bool isPatchPoint, bool hasNest, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &Ops, std::vector< EVT > &NodeTys, ImmutableCallSite CS, const PPCSubtarget &Subtarget)

static SDValue	widenVec (SelectionDAG &DAG, SDValue Vec, const SDLoc &dl)

static SDValue	BuildSplatI (int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	BuildSplatI - Build a canonical splati of Val with an element size of SplatSize. More...

static SDValue	BuildIntrinsicOp (unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
	BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID. More...

static SDValue	BuildIntrinsicOp (unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
	BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID. More...

static SDValue	BuildIntrinsicOp (unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
	BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID. More...

static SDValue	BuildVSLDOI (SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount. More...

static bool	haveEfficientBuildVectorPattern (BuildVectorSDNode *V, bool HasDirectMove, bool HasP8Vector)
	Do we have an efficient pattern in a .td file for this node? More...

static SDValue	GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
	GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More...

static bool	getVectorCompareInfo (SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget)
	getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison. More...

static Instruction *	callIntrinsic (IRBuilder<> &Builder, Intrinsic::ID Id)

static int	getEstimateRefinementSteps (EVT VT, const PPCSubtarget &Subtarget)

static void	getBaseWithConstantOffset (SDValue Loc, SDValue &Base, int64_t &Offset, SelectionDAG &DAG)

static bool	isConsecutiveLSLoc (SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)

static bool	isConsecutiveLS (SDNode N, LSBaseSDNode Base, unsigned Bytes, int Dist, SelectionDAG &DAG)

static bool	findConsecutiveLoad (LoadSDNode *LD, SelectionDAG &DAG)

static SDValue	generateEquivalentSub (SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG)
	This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR. More...

static bool	isFPExtLoad (SDValue Op)

static SDValue	combineBVOfConsecutiveLoads (SDNode *N, SelectionDAG &DAG)
	Reduce the number of loads when building a vector. More...

static SDValue	addShuffleForVecExtend (SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems)

static SDValue	combineBVOfVecSExt (SDNode *N, SelectionDAG &DAG)

static SDValue	stripModuloOnShift (const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG)

static SDValue	combineADDToADDZE (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)

Variables
static cl::opt< bool >	DisablePPCPreinc ("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)

static cl::opt< bool >	DisableILPPref ("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)

static cl::opt< bool >	DisablePPCUnaligned ("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)

static cl::opt< bool >	DisableSCO ("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)

static cl::opt< bool >	EnableQuadPrecision ("enable-ppc-quad-precision", cl::desc("enable quad precision float support on ppc"), cl::Hidden)

cl::opt< bool >	ANDIGlueBug

static const MCPhysReg	FPR []
	FPR - The set of FP registers that should be allocated for arguments, on Darwin. More...

static const MCPhysReg	QFPR []
	QFPR - The set of QPX registers that should be allocated for arguments. More...

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "ppc-lowering"

Definition at line 100 of file PPCISelLowering.cpp.

Function Documentation

◆ addShuffleForVecExtend()

static SDValue addShuffleForVecExtend	(	SDNode *	N,
		SelectionDAG &	DAG,
		SDValue	Input,
		uint64_t	Elems,
		uint64_t	CorrectElems
	)

static

Definition at line 12145 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::DataLayout::isLittleEndian(), and llvm::PPCISD::SExtVElems.

Referenced by combineBVOfVecSExt().

◆ areCallingConvEligibleForTCO_64SVR4()

static bool areCallingConvEligibleForTCO_64SVR4	(	CallingConv::ID	CallerCC,
		CallingConv::ID	CalleeCC
	)

static

◆ BuildIntrinsicOp() [1/3]

static SDValue BuildIntrinsicOp	(	unsigned	IID,
		SDValue	Op,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT	DestVT = `MVT::Other`
	)

static

BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.

Definition at line 7788 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

Referenced by getVectorCompareInfo(), haveEfficientBuildVectorPattern(), and llvm::PPCTargetLowering::PerformDAGCombine().

◆ BuildIntrinsicOp() [2/3]

static SDValue BuildIntrinsicOp	(	unsigned	IID,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT	DestVT = `MVT::Other`
	)

static

BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID.

Definition at line 7797 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

◆ BuildIntrinsicOp() [3/3]

static SDValue BuildIntrinsicOp	(	unsigned	IID,
		SDValue	Op0,
		SDValue	Op1,
		SDValue	Op2,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT	DestVT = `MVT::Other`
	)

static

BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID.

Definition at line 7807 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

◆ BuildSplatI()

static SDValue BuildSplatI	(	int	Val,
		unsigned	SplatSize,
		EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	dl
	)

static

BuildSplatI - Build a canonical splati of Val with an element size of SplatSize.

Cast the result to VT.

Definition at line 7766 of file PPCISelLowering.cpp.

References assert(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::Other, llvm::MVT::v16i8, llvm::MVT::v4i32, and llvm::MVT::v8i16.

Referenced by getVectorCompareInfo(), and haveEfficientBuildVectorPattern().

◆ BuildVSLDOI()

static SDValue BuildVSLDOI	(	SDValue	LHS,
		SDValue	RHS,
		unsigned	Amt,
		EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	dl
	)

static

BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.

The result has the specified value type.

Definition at line 7817 of file PPCISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), and llvm::MVT::v16i8.

Referenced by GeneratePerfectShuffle(), and haveEfficientBuildVectorPattern().

◆ CalculateStackSlotAlignment()

static unsigned CalculateStackSlotAlignment	(	EVT	ArgVT,
		EVT	OrigVT,
		ISD::ArgFlagsTy	Flags,
		unsigned	PtrByteSize
	)

static

CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack.

Definition at line 3274 of file PPCISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::MVT::f128, llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::EVT::getStoreSize(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegs(), llvm::ISD::ArgFlagsTy::isSplit(), llvm_unreachable, llvm::MVT::ppcf128, llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::MVT::v8i16.

Referenced by CalculateStackSlotUsed(), EnsureStackAlignment(), and PrepareCall().

◆ CalculateStackSlotSize()

static unsigned CalculateStackSlotSize	(	EVT	ArgVT,
		ISD::ArgFlagsTy	Flags,
		unsigned	PtrByteSize
	)

static

CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.

Definition at line 3258 of file PPCISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValSize(), llvm::EVT::getStoreSize(), llvm::ISD::ArgFlagsTy::isByVal(), and llvm::ISD::ArgFlagsTy::isInConsecutiveRegs().

Referenced by CalculateStackSlotUsed(), EnsureStackAlignment(), and PrepareCall().

◆ CalculateStackSlotUsed()

static bool CalculateStackSlotUsed	(	EVT	ArgVT,
		EVT	OrigVT,
		ISD::ArgFlagsTy	Flags,
		unsigned	PtrByteSize,
		unsigned	LinkageSize,
		unsigned	ParamAreaSize,
		unsigned &	ArgOffset,
		unsigned &	AvailableFPRs,
		unsigned &	AvailableVRs,
		bool	HasQPX
	)

static

CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers).

ArgOffset, AvailableFPRs, and AvailableVRs must hold the current argument position, and will be updated to account for this argument.

Definition at line 3320 of file PPCISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, CalculateStackSlotAlignment(), CalculateStackSlotSize(), llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegsLast(), llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::MVT::v8i16.

Referenced by EnsureStackAlignment(), needStackSlotPassParameters(), and PrepareCall().

◆ CalculateTailCallArgDest()

static void CalculateTailCallArgDest	(	SelectionDAG &	DAG,
		MachineFunction &	MF,
		bool	isPPC64,
		SDValue	Arg,
		int	SPDiff,
		unsigned	ArgOffset,
		SmallVectorImpl< TailCallArgumentInfo > &	TailCallArguments
	)

static

CalculateTailCallArgDest - Remember Argument for later processing.

Calculate the position of the argument.

Definition at line 4793 of file PPCISelLowering.cpp.

References Arg, llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SDValue::getValueSizeInBits(), llvm::MVT::i32, llvm::MVT::i64, Info, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by LowerMemOpCallTo(), and PrepareCall().

◆ CalculateTailCallSPDiff()

static int CalculateTailCallSPDiff	(	SelectionDAG &	DAG,
		bool	isTailCall,
		unsigned	ParamSize
	)

static

CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall.

Definition at line 4431 of file PPCISelLowering.cpp.

References Callee, llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::PPCFunctionInfo::getMinReservedArea(), isFunctionGlobalAddress(), and llvm::PPCFunctionInfo::setTailCallSPDelta().

Referenced by PrepareCall().

◆ callIntrinsic()

static Instruction* callIntrinsic	(	IRBuilder<> &	Builder,
		Intrinsic::ID	Id
	)

static

Definition at line 9750 of file PPCISelLowering.cpp.

References llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::BasicBlock::getParent(), and llvm::GlobalValue::getParent().

Referenced by llvm::PPCTargetLowering::emitLeadingFence(), and llvm::PPCTargetLowering::emitTrailingFence().

◆ callsShareTOCBase()

static bool callsShareTOCBase	(	const Function *	Caller,
		SDValue	Callee,
		const TargetMachine &	TM
	)

static

◆ combineADDToADDZE()

static SDValue combineADDToADDZE	(	SDNode *	N,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget
	)

static

Definition at line 14446 of file PPCISelLowering.cpp.

References llvm::ISD::ABS, llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, areCallingConvEligibleForTCO_64SVR4(), assert(), llvm::MCID::Bitcast, llvm::ISD::BITCAST, DisableSCO, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::CallBase::getCalledFunction(), llvm::Function::getCallingConv(), llvm::CallBase::getCallingConv(), llvm::SelectionDAG::getConstant(), llvm::Function::getFnAttribute(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::SelectionDAG::getTargetConstant(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::SDValue::hasOneUse(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::isInt< 16 >(), llvm::PPCSubtarget::isPPC64(), llvm::CallInst::isTailCall(), llvm::isUInt< 16 >(), llvm::Function::isVarArg(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::TargetMachine::shouldAssumeDSOLocal(), llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::SUBC, std::swap(), llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::PPCISD::VABSD, llvm::ISD::VSELECT, llvm::Z, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.

◆ combineBVOfConsecutiveLoads()

static SDValue combineBVOfConsecutiveLoads	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Reduce the number of loads when building a vector.

Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. If the loads are consecutive but in descending order, a shuffle is added at the end to reorder the vector.

Definition at line 12060 of file PPCISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::ISD::EXTLOAD, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), isConsecutiveLS(), llvm::ARM_MB::LD, llvm::MipsISD::LDL, llvm::SPII::Load, llvm::ISD::LOAD, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by combineBVOfVecSExt().

◆ combineBVOfVecSExt()

static SDValue combineBVOfVecSExt	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 12179 of file PPCISelLowering.cpp.

References addShuffleForVecExtend(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BUILD_VECTOR, combineBVOfConsecutiveLoads(), llvm::dyn_cast(), llvm::MipsISD::Ext, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::PPCISD::FCFID, llvm::PPCISD::FCFIDS, llvm::PPCISD::FCFIDU, llvm::PPCISD::FCFIDUS, llvm::PPCISD::FCTIDUZ, llvm::PPCISD::FCTIDZ, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::DataLayout::isLittleEndian(), llvm::ISD::LOAD, llvm::PPCISD::LXSIZX, llvm::PPCISD::MFVSR, llvm::MVT::Other, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, Signed, llvm::ISD::SINT_TO_FP, llvm::PPCISD::SINT_VEC_TO_FP, llvm::ISD::UINT_TO_FP, llvm::PPCISD::UINT_VEC_TO_FP, llvm::PPCTargetLowering::useSoftFloat(), llvm::MVT::v2f64, and llvm::PPCISD::VEXTS.

◆ CreateCopyOfByValArgument()

static SDValue CreateCopyOfByValArgument	(	SDValue	Src,
		SDValue	Dst,
		SDValue	Chain,
		ISD::ArgFlagsTy	Flags,
		SelectionDAG &	DAG,
		const SDLoc &	dl
	)

static

CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size".

Alignment information is specified by the specific parameter attribute. The copy will be passed as a byval function parameter. Sometimes what we are copying is the end of a larger object, the part that does not fit in registers.

Definition at line 4838 of file PPCISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), and llvm::MVT::i32.

Referenced by PrepareCall().

◆ EmitTailCallStoreFPAndRetAddr()

static SDValue EmitTailCallStoreFPAndRetAddr	(	SelectionDAG &	DAG,
		SDValue	Chain,
		SDValue	OldRetAddr,
		SDValue	OldFP,
		int	SPDiff,
		const SDLoc &	dl
	)

static

EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call.

Definition at line 4757 of file PPCISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::PPCSubtarget::getFrameLowering(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), llvm::MachineFunction::getSubtarget(), llvm::MVT::i32, llvm::MVT::i64, llvm::PPCSubtarget::isDarwinABI(), and llvm::PPCSubtarget::isPPC64().

Referenced by PrepareTailCall().

◆ EnsureStackAlignment()

static unsigned EnsureStackAlignment	(	const PPCFrameLowering *	Lowering,
		unsigned	NumBytes
	)

static

EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target.

Definition at line 3375 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::MachineFunction::addLiveIn(), llvm::PPCFunctionInfo::addLiveInAttr(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::CCState::AllocateStack(), Arg, llvm::Function::arg_begin(), llvm::array_lengthof(), assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BITCAST, CalculateStackSlotAlignment(), CalculateStackSlotSize(), CalculateStackSlotUsed(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::CreateStackObject(), llvm::Depth, llvm::SmallVectorBase::empty(), llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::CallingConv::Fast, llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::PPCSubtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::PPCFrameLowering::getLinkageSize(), llvm::MachineRegisterInfo::getLiveInVirtReg(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::getSizeInBits(), llvm::TargetFrameLowering::getStackAlignment(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSize(), llvm::MVT::getStoreSize(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SelectionDAG::getTruncStore(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::CCValAssign::getValVT(), llvm::PPCFunctionInfo::getVarArgsFrameIndex(), llvm::GPR, llvm::TargetOptions::GuaranteedTailCallOpt, llvm::PPCSubtarget::hasP8Vector(), llvm::PPCSubtarget::hasQPX(), llvm::PPCSubtarget::hasSPE(), llvm::PPCTargetLowering::hasSPE(), llvm::PPCSubtarget::hasVSX(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MipsISD::Ins, llvm::ISD::ArgFlagsTy::isByVal(), llvm::PPCSubtarget::isELFv2ABI(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegs(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegsLast(), llvm::PPCSubtarget::isLittleEndian(), llvm::CCValAssign::isMemLoc(), llvm::ISD::ArgFlagsTy::isNest(), llvm::PPCSubtarget::isPPC64(), llvm::CCValAssign::isRegLoc(), llvm::ISD::ArgFlagsTy::isSExt(), llvm::PPCSubtarget::isSVR4ABI(), llvm::ISD::ArgFlagsTy::isZExt(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::max(), llvm::TargetMachine::Options, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), R4, R6, Reg, llvm::PPCFunctionInfo::setMinReservedArea(), llvm::PPCFunctionInfo::setVarArgsFrameIndex(), llvm::PPCFunctionInfo::setVarArgsNumFPR(), llvm::PPCFunctionInfo::setVarArgsNumGPR(), llvm::PPCFunctionInfo::setVarArgsStackOffset(), llvm::MVT::SimpleTy, llvm::SmallVectorBase::size(), llvm::ISD::SRL, llvm::SPII::Store, llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, llvm::PPCTargetLowering::useSoftFloat(), llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::NVPTX::PTXLdStInstCode::V4, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::MVT::v8i16.

Referenced by PrepareCall().

◆ findConsecutiveLoad()

static bool findConsecutiveLoad	(	LoadSDNode *	LD,
		SelectionDAG &	DAG
	)

static

◆ fixupFuncForFI()

static void fixupFuncForFI	(	SelectionDAG &	DAG,
		int	FrameIdx,
		EVT	VT
	)

static

Definition at line 2253 of file PPCISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MVT::i64, and llvm::PPCFunctionInfo::setHasNonRISpills().

Referenced by llvm::PPCTargetLowering::SelectAddressRegImm().

◆ generateEquivalentSub()

static SDValue generateEquivalentSub	(	SDNode *	N,
		int	Size,
		bool	Complement,
		bool	Swap,
		SDLoc &	DL,
		SelectionDAG &	DAG
	)

static

This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR.

This function is purely for codegen purposes and has some flags to guide the codegen process.

Definition at line 11289 of file PPCISelLowering.cpp.

◆ GeneratePerfectShuffle()

static SDValue GeneratePerfectShuffle	(	unsigned	PFEntry,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	dl
	)

static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 8204 of file PPCISelLowering.cpp.

◆ getBaseWithConstantOffset()

static void getBaseWithConstantOffset	(	SDValue	Loc,
		SDValue &	Base,
		int64_t &	Offset,
		SelectionDAG &	DAG
	)

static

Definition at line 11057 of file PPCISelLowering.cpp.

References llvm::SDValue::getOperand(), and llvm::SelectionDAG::isBaseWithConstantOffset().

Referenced by isConsecutiveLSLoc().

◆ getEstimateRefinementSteps()

static int getEstimateRefinementSteps	(	EVT	VT,
		const PPCSubtarget &	Subtarget
	)

static

Definition at line 10984 of file PPCISelLowering.cpp.

References llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::TargetLoweringBase::Enabled, llvm::MVT::f32, llvm::MVT::f64, llvm::PPCISD::FRE, llvm::PPCISD::FRSQRTE, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::PPCSubtarget::hasRecipPrec(), llvm::MVT::v2f64, llvm::MVT::v4f32, and llvm::MVT::v4f64.

◆ getLabelAccessInfo()

static void getLabelAccessInfo	(	bool	IsPIC,
		const PPCSubtarget &	Subtarget,
		unsigned &	HiOpFlags,
		unsigned &	LoOpFlags,
		const GlobalValue *	GV = `nullptr`
	)

static

Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.

Definition at line 2536 of file PPCISelLowering.cpp.

References llvm::PPCSubtarget::hasLazyResolverStub(), llvm::PPCII::MO_HA, llvm::PPCII::MO_LO, llvm::PPCII::MO_NLP_FLAG, llvm::PPCII::MO_NLP_HIDDEN_FLAG, and llvm::PPCII::MO_PIC_FLAG.

Referenced by llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), and getTOCEntry().

◆ getMaxByValAlign()

static void getMaxByValAlign	(	Type *	Ty,
		unsigned &	MaxAlign,
		unsigned	MaxMaxAlign
	)

static

getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.

Definition at line 1193 of file PPCISelLowering.cpp.

Referenced by llvm::PPCTargetLowering::getByValTypeAlignment().

◆ getTOCEntry()

static SDValue getTOCEntry	(	SelectionDAG &	DAG,
		const SDLoc &	dl,
		bool	Is64Bit,
		SDValue	GA
	)

static

Definition at line 2589 of file PPCISelLowering.cpp.

References C, llvm::HexagonISD::CP, llvm::ConstantPoolSDNode::getAlignment(), llvm::ConstantPoolSDNode::getConstVal(), llvm::MachinePointerInfo::getGOT(), getLabelAccessInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::PPCISD::GlobalBaseReg, llvm::MVT::i32, llvm::MVT::i64, llvm::TargetLowering::isPositionIndependent(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isSVR4ABI(), LowerLabelRef(), llvm::PPCII::MO_PIC_FLAG, llvm::MachineMemOperand::MOLoad, llvm::MVT::Other, Reg, setUsesTOCBasePtr(), and llvm::PPCISD::TOC_ENTRY.

Referenced by llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr().

◆ getVectorCompareInfo()

static bool getVectorCompareInfo	(	SDValue	Intrin,
		int &	CompareOpc,
		bool &	isDot,
		const PPCSubtarget &	Subtarget
	)

static

getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.

If it is, return true and fill in Opc/isDot with information about the intrinsic.

Definition at line 8773 of file PPCISelLowering.cpp.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ hasSameArgumentList()

static bool hasSameArgumentList	(	const Function *	CallerFn,
		ImmutableCallSite	CS
	)

static

Definition at line 4545 of file PPCISelLowering.cpp.

References llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::arg_begin(), llvm::Function::arg_begin(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::arg_end(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::arg_size(), llvm::Function::arg_size(), and llvm::Value::getType().

Referenced by areCallingConvEligibleForTCO_64SVR4().

◆ haveEfficientBuildVectorPattern()

static bool haveEfficientBuildVectorPattern	(	BuildVectorSDNode *	V,
		bool	HasDirectMove,
		bool	HasP8Vector
	)

static

Do we have an efficient pattern in a .td file for this node?

Parameters

V	- pointer to the BuildVectorSDNode being matched
HasDirectMove	- does this subtarget have VSR <-> GPR direct moves?

There are some patterns where it is beneficial to keep a BUILD_VECTOR node as a BUILD_VECTOR node rather than expanding it. The patterns where the opposite is true (expansion is beneficial) are:

The node builds a vector out of integers that are not 32 or 64-bits
The node builds a vector out of constants
The node is a "load-and-splat" In all other cases, we will choose to keep the BUILD_VECTOR.

Definition at line 7842 of file PPCISelLowering.cpp.

◆ isBLACompatibleAddress()

static SDNode* isBLACompatibleAddress	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction.

Definition at line 4711 of file PPCISelLowering.cpp.

References Arg, C, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ConstantSDNode::getZExtValue().

Referenced by PrepareCall().

◆ isConsecutiveLS()

static bool isConsecutiveLS	(	SDNode *	N,
		LSBaseSDNode *	Base,
		unsigned	Bytes,
		int	Dist,
		SelectionDAG &	DAG
	)

static

Definition at line 11109 of file PPCISelLowering.cpp.

Referenced by combineBVOfConsecutiveLoads(), and findConsecutiveLoad().

◆ isConsecutiveLSLoc()

static bool isConsecutiveLSLoc	(	SDValue	Loc,
		EVT	VT,
		LSBaseSDNode *	Base,
		unsigned	Bytes,
		int	Dist,
		SelectionDAG &	DAG
	)

static

Definition at line 11069 of file PPCISelLowering.cpp.

References llvm::AMDGPUISD::BFI, llvm::ISD::FrameIndex, llvm::MemSDNode::getBasePtr(), getBaseWithConstantOffset(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::TargetLowering::isGAPlusOffset().

Referenced by isConsecutiveLS().

◆ isConstantOrUndef()

static bool isConstantOrUndef	(	int	Op,
		int	Val
	)

static

isConstantOrUndef - Op is either an undef node or a ConstantSDNode.

Return true if Op is undef or if it matches the specified value.

Definition at line 1408 of file PPCISelLowering.cpp.

Referenced by llvm::PPC::isQVALIGNIShuffleMask(), isVMerge(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), and llvm::PPC::isVSLDOIShuffleMask().

◆ isFloatingPointZero()

static bool isFloatingPointZero ( SDValue Op )

static

isFloatingPointZero - Return true if this is 0.0 or -0.0.

Definition at line 1394 of file PPCISelLowering.cpp.

References llvm::HexagonISD::CP, llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::ISD::isEXTLoad(), and llvm::ISD::isNON_EXTLoad().

Referenced by PrepareCall().

◆ isFPExtLoad()

static bool isFPExtLoad ( SDValue Op )

static

◆ isFunctionGlobalAddress()

static bool isFunctionGlobalAddress ( SDValue Callee )

static

Definition at line 4898 of file PPCISelLowering.cpp.

References G, llvm::SDValue::getOpcode(), llvm::ISD::GlobalTLSAddress, and llvm::ISD::TargetGlobalTLSAddress.

Referenced by areCallingConvEligibleForTCO_64SVR4(), CalculateTailCallSPDiff(), and PrepareCall().

◆ isNByteElemShuffleMask()

static bool isNByteElemShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	Width,
		int	StepLen
	)

static

Check that the mask is shuffling N byte elements.

Within each N byte element of the mask, the indices could be either in increasing or decreasing order as long as they are consecutive.

Parameters

[in]	N	the shuffle vector SD Node to analyze
[in]	Width	the element width in bytes, could be 2/4/8/16 (HalfWord/ Word/DoubleWord/QuadWord).
[in]	StepLen	the delta indices number among the N byte element, if the mask is in increasing/decreasing order then it is 1/-1.

Returns: true iff the mask is shuffling N byte elements.

Definition at line 1783 of file PPCISelLowering.cpp.

References assert(), and llvm::ShuffleVectorSDNode::getMaskElt().

Referenced by GeneratePerfectShuffle(), isXXBRShuffleMaskHelper(), llvm::PPC::isXXINSERTWMask(), llvm::PPC::isXXPERMDIShuffleMask(), and llvm::PPC::isXXSLDWIShuffleMask().

◆ isVMerge() [1/2]

static bool isVMerge	(	ShuffleVectorSDNode *	N,
		unsigned	UnitSize,
		unsigned	LHSStart,
		unsigned	RHSStart
	)

static

isVMerge - Common function, used to match vmrg* shuffles.

Definition at line 1530 of file PPCISelLowering.cpp.

References assert(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isConstantOrUndef(), and llvm::MVT::v16i8.

Referenced by llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), and llvm::PPC::isVMRGLShuffleMask().

◆ isVMerge() [2/2]

static bool isVMerge	(	ShuffleVectorSDNode *	N,
		unsigned	IndexOffset,
		unsigned	RHSStartValue
	)

static

Common function used to match vmrgew and vmrgow shuffles.

The indexOffset determines whether to look for even or odd words in the shuffle mask. This is based on the of the endianness of the target machine.

Little Endian:
- Use offset of 0 to check for odd elements
- Use offset of 4 to check for even elements
Big Endian:
- Use offset of 0 to check for even elements
- Use offset of 4 to check for odd elements A detailed description of the vector element ordering for little endian and big endian can be found at http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html Targeting your applications - what little endian and big endian IBM XL C/C++ compiler differences mean to you

The mask to the shuffle vector instruction specifies the indices of the elements from the two input vectors to place in the result. The elements are numbered in array-access order, starting with the first vector. These vectors are always of type v16i8, thus each vector will contain 16 elements of size

More info on the shuffle vector can be found in the http://llvm.org/docs/LangRef.html#shufflevector-instruction Language Reference.

The RHSStartValue indicates whether the same input vectors are used (unary) or two different input vectors are used, based on the following:

If the instruction uses the same vector for both inputs, the range of the indices will be 0 to 15. In this case, the RHSStart value passed should be 0.
If the instruction has two different vectors then the range of the indices will be 0 to 31. In this case, the RHSStart value passed should be 16 (indices 0-15 specify elements in the first vector while indices 16 to 31 specify elements in the second vector).

Parameters

[in]	N	The shuffle vector SD Node to analyze
[in]	IndexOffset	Specifies whether to look for even or odd elements
[in]	RHSStartValue	Specifies the starting index for the righthand input vector to the shuffle_vector instruction

Returns: true iff this shuffle vector represents an even or odd word merge

Definition at line 1640 of file PPCISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isConstantOrUndef(), and llvm::MVT::v16i8.

◆ isXXBRShuffleMaskHelper()

static bool isXXBRShuffleMaskHelper	(	ShuffleVectorSDNode *	N,
		int	Width
	)

static

Definition at line 1947 of file PPCISelLowering.cpp.

References assert(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isNByteElemShuffleMask(), and llvm::MVT::v16i8.

Referenced by llvm::PPC::isXXBRDShuffleMask(), llvm::PPC::isXXBRHShuffleMask(), llvm::PPC::isXXBRQShuffleMask(), and llvm::PPC::isXXBRWShuffleMask().

◆ LowerLabelRef()

static SDValue LowerLabelRef	(	SDValue	HiPart,
		SDValue	LoPart,
		bool	isPIC,
		SelectionDAG &	DAG
	)

static

Definition at line 2561 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::PPCISD::GlobalBaseReg, llvm::MipsISD::Hi, llvm::PPCISD::Hi, llvm::MipsISD::Lo, and llvm::PPCISD::Lo.

Referenced by llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), and getTOCEntry().

◆ LowerMemOpCallTo()

static void LowerMemOpCallTo	(	SelectionDAG &	DAG,
		MachineFunction &	MF,
		SDValue	Chain,
		SDValue	Arg,
		SDValue	PtrOff,
		int	SPDiff,
		unsigned	ArgOffset,
		bool	isPPC64,
		bool	isTailCall,
		bool	isVector,
		SmallVectorImpl< SDValue > &	MemOpChains,
		SmallVectorImpl< TailCallArgumentInfo > &	TailCallArguments,
		const SDLoc &	dl
	)

static

LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.

Definition at line 4849 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, CalculateTailCallArgDest(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i32, llvm::MVT::i64, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::X86TargetLowering::getMaxSupportedInterleaveFactor(), llvm::ARMTargetLowering::hasStandaloneRem(), and PrepareCall().

◆ needStackSlotPassParameters()

static bool needStackSlotPassParameters	(	const PPCSubtarget &	Subtarget,
		const SmallVectorImpl< ISD::OutputArg > &	Outs
	)

static

Definition at line 4507 of file PPCISelLowering.cpp.

References llvm::array_lengthof(), assert(), CalculateStackSlotUsed(), llvm::PPCSubtarget::getFrameLowering(), llvm::PPCFrameLowering::getLinkageSize(), llvm::GPR, llvm::PPCSubtarget::hasQPX(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isSVR4ABI(), llvm::NVPTX::PTXLdStInstCode::V2, and llvm::NVPTX::PTXLdStInstCode::V4.

Referenced by areCallingConvEligibleForTCO_64SVR4().

◆ PrepareCall()

static unsigned PrepareCall	(	SelectionDAG &	DAG,
		SDValue &	Callee,
		SDValue &	InFlag,
		SDValue &	Chain,
		SDValue	CallSeqStart,
		const SDLoc &	dl,
		int	SPDiff,
		bool	isTailCall,
		bool	isPatchPoint,
		bool	hasNest,
		SmallVectorImpl< std::pair< unsigned, SDValue >> &	RegsToPass,
		SmallVectorImpl< SDValue > &	Ops,
		std::vector< EVT > &	NodeTys,
		ImmutableCallSite	CS,
		const PPCSubtarget &	Subtarget
	)

static

Definition at line 4911 of file PPCISelLowering.cpp.

◆ PrepareTailCall()

static void PrepareTailCall	(	SelectionDAG &	DAG,
		SDValue &	InFlag,
		SDValue &	Chain,
		const SDLoc &	dl,
		int	SPDiff,
		unsigned	NumBytes,
		SDValue	LROp,
		SDValue	FPOp,
		SmallVectorImpl< TailCallArgumentInfo > &	TailCallArguments
	)

static

Definition at line 4873 of file PPCISelLowering.cpp.

References EmitTailCallStoreFPAndRetAddr(), llvm::SmallVectorBase::empty(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::MVT::Other, StoreTailCallArgumentsToStackSlot(), and llvm::ISD::TokenFactor.

Referenced by PrepareCall().

◆ setUsesTOCBasePtr() [1/2]

static void setUsesTOCBasePtr ( MachineFunction & MF )

static

Definition at line 2580 of file PPCISelLowering.cpp.

References llvm::MachineFunction::getInfo(), and llvm::PPCFunctionInfo::setUsesTOCBasePtr().

Referenced by llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getTOCEntry(), PrepareCall(), and setUsesTOCBasePtr().

◆ setUsesTOCBasePtr() [2/2]

static void setUsesTOCBasePtr ( SelectionDAG & DAG )

static

Definition at line 2585 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getMachineFunction(), and setUsesTOCBasePtr().

◆ STATISTIC() [1/2]

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

◆ STATISTIC() [2/2]

STATISTIC	(	NumSiblingCalls	,
		"Number of sibling calls"
	)

◆ StoreTailCallArgumentsToStackSlot()

static void StoreTailCallArgumentsToStackSlot	(	SelectionDAG &	DAG,
		SDValue	Chain,
		const SmallVectorImpl< TailCallArgumentInfo > &	TailCallArgs,
		SmallVectorImpl< SDValue > &	MemOpChains,
		const SDLoc &	dl
	)

static

StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.

Definition at line 4740 of file PPCISelLowering.cpp.

References Arg, llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::SmallVectorBase::size().

Referenced by PrepareTailCall().

◆ stripModuloOnShift()

static SDValue stripModuloOnShift	(	const TargetLowering &	TLI,
		SDNode *	N,
		SelectionDAG &	DAG
	)

static

◆ usePartialVectorLoads()

static bool usePartialVectorLoads ( SDNode * N )

static

Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence.

Definition at line 2419 of file PPCISelLowering.cpp.

References llvm::SDNode::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::hasOneUse(), llvm::MVT::i64, llvm::EVT::isSimple(), llvm::ARM_MB::LD, llvm::ISD::SCALAR_TO_VECTOR, and llvm::MVT::SimpleTy.

Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().

◆ widenVec()

static SDValue widenVec	(	SelectionDAG &	DAG,
		SDValue	Vec,
		const SDLoc &	dl
	)

static

Definition at line 7286 of file PPCISelLowering.cpp.

Variable Documentation

◆ ANDIGlueBug

cl::opt<bool> ANDIGlueBug

Referenced by mayUseP9Setb().

◆ DisableILPPref

cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)

static

Referenced by llvm::PPCTargetLowering::getSchedulingPreference().

◆ DisablePPCPreinc

cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)

static

Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().

◆ DisablePPCUnaligned

cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)

static

Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses().

◆ DisableSCO

cl::opt<bool> DisableSCO("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)

static

Referenced by areCallingConvEligibleForTCO_64SVR4(), and combineADDToADDZE().

◆ EnableQuadPrecision

cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision", cl::desc("enable quad precision float support on ppc"), cl::Hidden)

static

Referenced by haveEfficientBuildVectorPattern(), llvm::PPCTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::PPCTargetLowering::PPCTargetLowering(), PrepareCall(), and widenVec().

◆ FPR

const MCPhysReg FPR[]

static

Initial value:

= {PPC::F1,  PPC::F2,  PPC::F3, PPC::F4, PPC::F5,
                                PPC::F6,  PPC::F7,  PPC::F8, PPC::F9, PPC::F10,
                                PPC::F11, PPC::F12, PPC::F13}

FPR - The set of FP registers that should be allocated for arguments, on Darwin.

Definition at line 3247 of file PPCISelLowering.cpp.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), and llvm::SystemZMachineFunctionInfo::setVarArgsFirstFPR().

◆ QFPR

const MCPhysReg QFPR[]

static

Initial value:

= {
    PPC::QF1, PPC::QF2, PPC::QF3,  PPC::QF4,  PPC::QF5,  PPC::QF6, PPC::QF7,
    PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13}

QFPR - The set of QPX registers that should be allocated for arguments.

Definition at line 3252 of file PPCISelLowering.cpp.

Macros

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ addShuffleForVecExtend()

◆ areCallingConvEligibleForTCO_64SVR4()

◆ BuildIntrinsicOp() [1/3]

◆ BuildIntrinsicOp() [2/3]

◆ BuildIntrinsicOp() [3/3]

◆ BuildSplatI()

◆ BuildVSLDOI()

◆ CalculateStackSlotAlignment()

◆ CalculateStackSlotSize()

◆ CalculateStackSlotUsed()

◆ CalculateTailCallArgDest()

◆ CalculateTailCallSPDiff()

◆ callIntrinsic()

◆ callsShareTOCBase()

◆ combineADDToADDZE()

◆ combineBVOfConsecutiveLoads()

◆ combineBVOfVecSExt()

◆ CreateCopyOfByValArgument()

◆ EmitTailCallStoreFPAndRetAddr()

◆ EnsureStackAlignment()

◆ findConsecutiveLoad()

◆ fixupFuncForFI()

◆ generateEquivalentSub()

◆ GeneratePerfectShuffle()

◆ getBaseWithConstantOffset()

◆ getEstimateRefinementSteps()

◆ getLabelAccessInfo()

◆ getMaxByValAlign()

◆ getTOCEntry()

◆ getVectorCompareInfo()

◆ hasSameArgumentList()

◆ haveEfficientBuildVectorPattern()

◆ isBLACompatibleAddress()

◆ isConsecutiveLS()

◆ isConsecutiveLSLoc()

◆ isConstantOrUndef()

◆ isFloatingPointZero()

◆ isFPExtLoad()

◆ isFunctionGlobalAddress()

◆ isNByteElemShuffleMask()

◆ isVMerge() [1/2]

◆ isVMerge() [2/2]

◆ isXXBRShuffleMaskHelper()

◆ LowerLabelRef()

◆ LowerMemOpCallTo()

◆ needStackSlotPassParameters()

◆ PrepareCall()

◆ PrepareTailCall()

◆ setUsesTOCBasePtr() [1/2]

◆ setUsesTOCBasePtr() [2/2]

◆ STATISTIC() [1/2]

◆ STATISTIC() [2/2]

◆ StoreTailCallArgumentsToStackSlot()

◆ stripModuloOnShift()

◆ usePartialVectorLoads()

◆ widenVec()

Variable Documentation

◆ ANDIGlueBug

◆ DisableILPPref

◆ DisablePPCPreinc

◆ DisablePPCUnaligned

◆ DisableSCO

◆ EnableQuadPrecision

◆ FPR

◆ QFPR