#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMConstantPoolValue.h"
#include "ARMFeatures.h"
#include "ARMHazardRecognizer.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Triple.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <new>
#include <utility>
#include <vector>
#include "ARMGenInstrInfo.inc"

Classes
struct	ARM_MLxEntry
	ARM_MLxEntry - Record information about MLA / MLS instructions. More...

struct	AddSubFlagsOpcodePair
	Map pseudo instructions that imply an 'S' bit onto real opcodes. More...

Namespaces
	llvm
	This class represents lattice values for constants.

Macros
#define	DEBUG_TYPE "arm-instrinfo"

#define	GET_INSTRINFO_CTOR_DTOR

Enumerations
enum	ARMExeDomain { ExeGeneric = 0, ExeVFP = 1, ExeNEON = 2 }

Functions
static bool	isEligibleForITBlock (const MachineInstr *MI)

template<>
bool	llvm::IsCPSRDead< MachineInstr > (const MachineInstr *MI)

static unsigned	duplicateCPV (MachineFunction &MF, unsigned &CPI)
	Create a copy of a const pool value. More...

static MachineInstr *	canFoldIntoMOVCC (unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
	Identify instructions that can be folded into a MOVCC instruction, and return the defining instruction. More...

static bool	isSuitableForMask (MachineInstr *&MI, unsigned SrcReg, int CmpMask, bool CommonUse)
	isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register and applies the same mask as a 'tst' instruction. More...

static ARMCC::CondCodes	getSwappedCondition (ARMCC::CondCodes CC)
	getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a). More...

static ARMCC::CondCodes	getCmpToAddCondition (ARMCC::CondCodes CC)
	getCmpToAddCondition - assume the flags are set by CMP(a,b), return the condition code if we modify the instructions such that flags are set by ADD(a,b,X). More...

static bool	isRedundantFlagInstr (const MachineInstr CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, const MachineInstr OI)
	isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant. More...

static bool	isOptimizeCompareCandidate (MachineInstr *MI, bool &IsThumb1)

static unsigned	getNumMicroOpsSwiftLdSt (const InstrItineraryData *ItinData, const MachineInstr &MI)

static unsigned	getNumMicroOpsSingleIssuePlusExtras (unsigned Opc, unsigned NumRegs)

static const MachineInstr *	getBundledDefMI (const TargetRegisterInfo TRI, const MachineInstr MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist)

static const MachineInstr *	getBundledUseMI (const TargetRegisterInfo *TRI, const MachineInstr &MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist)

static int	adjustDefLatency (const ARMSubtarget &Subtarget, const MachineInstr &DefMI, const MCInstrDesc &DefMCID, unsigned DefAlign)
	Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode and alignment. More...

static unsigned	getCorrespondingDRegAndLane (const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane)

static bool	getImplicitSPRUseForDPRUse (const TargetRegisterInfo *TRI, MachineInstr &MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg)
	getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register number that must be marked as implicit-use or zero if no register needs to be defined as implicit-use. More...

Variables
static cl::opt< bool >	EnableARM3Addr ("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv"))

static const ARM_MLxEntry	ARM_MLxTable []

static const AddSubFlagsOpcodePair	AddSubFlagsOpcodeMap []

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-instrinfo"

Definition at line 69 of file ARMBaseInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 71 of file ARMBaseInstrInfo.cpp.

Enumeration Type Documentation

◆ ARMExeDomain

enum ARMExeDomain

Enumerator
ExeGeneric
ExeVFP
ExeNEON

Definition at line 4586 of file ARMBaseInstrInfo.cpp.

Function Documentation

◆ adjustDefLatency()

static int adjustDefLatency	(	const ARMSubtarget &	Subtarget,
		const MachineInstr &	DefMI,
		const MCInstrDesc &	DefMCID,
		unsigned	DefAlign
	)

static

Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode and alignment.

The caller will ensure that adjusted latency is at least one cycle.

Definition at line 3858 of file ARMBaseInstrInfo.cpp.

References llvm::ARMSubtarget::checkVLDnAccessAlignment(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::ARMSubtarget::isLikeA9(), llvm::ARMSubtarget::isSwift(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and llvm::ARM_AM::sub.

Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().

◆ canFoldIntoMOVCC()

static MachineInstr* canFoldIntoMOVCC	(	unsigned	Reg,
		const MachineRegisterInfo &	MRI,
		const TargetInstrInfo *	TII
	)

static

Identify instructions that can be folded into a MOVCC instruction, and return the defining instruction.

Definition at line 2043 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMBaseInstrInfo::optimizeSelect().

◆ duplicateCPV()

static unsigned duplicateCPV	(	MachineFunction &	MF,
		unsigned &	CPI
	)

static

Create a copy of a const pool value.

Update CPI to the new index and return the label UID.

Definition at line 1547 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::ARMCP::CPBlockAddress, llvm::ARMCP::CPLSDA, llvm::ARMCP::CPValue, llvm::ARMConstantPoolConstant::Create(), llvm::ARMFunctionInfo::createPICLabelUId(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineConstantPool::getConstants(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::object::getSymbol(), and llvm_unreachable.

Referenced by llvm::ARMBaseInstrInfo::duplicate(), and llvm::ARMBaseInstrInfo::reMaterialize().

◆ getBundledDefMI()

static const MachineInstr* getBundledDefMI	(	const TargetRegisterInfo *	TRI,
		const MachineInstr *	MI,
		unsigned	Reg,
		unsigned &	DefIdx,
		unsigned &	Dist
	)

static

Definition at line 3803 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), I, and MI.

Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().

◆ getBundledUseMI()

static const MachineInstr* getBundledUseMI	(	const TargetRegisterInfo *	TRI,
		const MachineInstr &	MI,
		unsigned	Reg,
		unsigned &	UseIdx,
		unsigned &	Dist
	)

static

Definition at line 3826 of file ARMBaseInstrInfo.cpp.

References assert(), E, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), and llvm::MachineBasicBlock::instr_end().

Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().

◆ getCmpToAddCondition()

static ARMCC::CondCodes getCmpToAddCondition ( ARMCC::CondCodes CC )

inlinestatic

getCmpToAddCondition - assume the flags are set by CMP(a,b), return the condition code if we modify the instructions such that flags are set by ADD(a,b,X).

Definition at line 2604 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::HS, llvm::ARMCC::LO, llvm::ARMCC::VC, and llvm::ARMCC::VS.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().

◆ getCorrespondingDRegAndLane()

static unsigned getCorrespondingDRegAndLane	(	const TargetRegisterInfo *	TRI,
		unsigned	SReg,
		unsigned &	Lane
	)

static

Definition at line 4629 of file ARMBaseInstrInfo.cpp.

References assert(), and llvm::TargetRegisterInfo::getMatchingSuperReg().

Referenced by llvm::ARMBaseInstrInfo::setExecutionDomain().

◆ getImplicitSPRUseForDPRUse()

static bool getImplicitSPRUseForDPRUse	(	const TargetRegisterInfo *	TRI,
		MachineInstr &	MI,
		unsigned	DReg,
		unsigned	Lane,
		unsigned &	ImplicitSReg
	)

static

getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register number that must be marked as implicit-use or zero if no register needs to be defined as implicit-use.

If the function cannot determine if an SPR should be marked implicit use or not, it returns false.

This function handles cases where an instruction is being modified from taking an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict with an earlier def of an SPR corresponding to DPRLane^1.

If the other SPR is defined, an implicit-use of it should be added. Else, (including the case where the DPR itself is defined), it should not.

Definition at line 4659 of file ARMBaseInstrInfo.cpp.

References llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::getParent(), llvm::MCRegisterInfo::getSubReg(), llvm::MachineBasicBlock::LQR_Live, llvm::MachineBasicBlock::LQR_Unknown, and llvm::MachineInstr::readsRegister().

Referenced by llvm::ARMBaseInstrInfo::setExecutionDomain().

◆ getNumMicroOpsSingleIssuePlusExtras()

static unsigned getNumMicroOpsSingleIssuePlusExtras	(	unsigned	Opc,
		unsigned	NumRegs
	)

static

Definition at line 3378 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().

◆ getNumMicroOpsSwiftLdSt()

static unsigned getNumMicroOpsSwiftLdSt	(	const InstrItineraryData *	ItinData,
		const MachineInstr &	MI
	)

static

Definition at line 3120 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::InstrItineraryData::getNumMicroOps(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MCInstrDesc::getSchedClass(), llvm::ARM_AM::lsl, and llvm::ARM_AM::sub.

Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().

◆ getSwappedCondition()

static ARMCC::CondCodes getSwappedCondition ( ARMCC::CondCodes CC )

inlinestatic

getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).

Definition at line 2585 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ARMCC::NE.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().

◆ isEligibleForITBlock()

static bool isEligibleForITBlock ( const MachineInstr * MI )

static

Definition at line 623 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and llvm::ARMBaseInstrInfo::isCPSRDefined().

Referenced by llvm::ARMBaseInstrInfo::isPredicable().

◆ isOptimizeCompareCandidate()

static bool isOptimizeCompareCandidate	(	MachineInstr *	MI,
		bool &	IsThumb1
	)

static

Definition at line 2651 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and LLVM_FALLTHROUGH.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().

◆ isRedundantFlagInstr()

static bool isRedundantFlagInstr	(	const MachineInstr *	CmpI,
		unsigned	SrcReg,
		unsigned	SrcReg2,
		int	ImmValue,
		const MachineInstr *	OI
	)

inlinestatic

isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant.

CMPrr can be made redundant by SUBrr if the operands are the same. CMPri can be made redundant by SUBri if the operands are the same. CMPrr(r0, r1) can be made redundant by ADDr[ri](r0, r1, X). This function can be extended later on.

Definition at line 2620 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr(), and llvm::ARMBaseInstrInfo::shouldSink().

◆ isSuitableForMask()

static bool isSuitableForMask	(	MachineInstr *&	MI,
		unsigned	SrcReg,
		int	CmpMask,
		bool	CommonUse
	)

static

isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register and applies the same mask as a 'tst' instruction.

Provide a limited look-through for copies. When successful, MI will hold the found instruction.

Definition at line 2567 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().

Variable Documentation

◆ AddSubFlagsOpcodeMap

const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[]

static

Definition at line 2178 of file ARMBaseInstrInfo.cpp.

◆ ARM_MLxTable

const ARM_MLxEntry ARM_MLxTable[]

static

Initial value:

= {
  
  
  { ARM::VMLAS,       ARM::VMULS,       ARM::VADDS,      false,  false },
  { ARM::VMLSS,       ARM::VMULS,       ARM::VSUBS,      false,  false },
  { ARM::VMLAD,       ARM::VMULD,       ARM::VADDD,      false,  false },
  { ARM::VMLSD,       ARM::VMULD,       ARM::VSUBD,      false,  false },
  { ARM::VNMLAS,      ARM::VNMULS,      ARM::VSUBS,      true,   false },
  { ARM::VNMLSS,      ARM::VMULS,       ARM::VSUBS,      true,   false },
  { ARM::VNMLAD,      ARM::VNMULD,      ARM::VSUBD,      true,   false },
  { ARM::VNMLSD,      ARM::VMULD,       ARM::VSUBD,      true,   false },
  
  { ARM::VMLAfd,      ARM::VMULfd,      ARM::VADDfd,     false,  false },
  { ARM::VMLSfd,      ARM::VMULfd,      ARM::VSUBfd,     false,  false },
  { ARM::VMLAfq,      ARM::VMULfq,      ARM::VADDfq,     false,  false },
  { ARM::VMLSfq,      ARM::VMULfq,      ARM::VSUBfq,     false,  false },
  { ARM::VMLAslfd,    ARM::VMULslfd,    ARM::VADDfd,     false,  true  },
  { ARM::VMLSslfd,    ARM::VMULslfd,    ARM::VSUBfd,     false,  true  },
  { ARM::VMLAslfq,    ARM::VMULslfq,    ARM::VADDfq,     false,  true  },
  { ARM::VMLSslfq,    ARM::VMULslfq,    ARM::VSUBfq,     false,  true  },
}

Definition at line 87 of file ARMBaseInstrInfo.cpp.

◆ EnableARM3Addr

cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv"))

static

Referenced by llvm::ARMBaseInstrInfo::convertToThreeAddress().

Classes

Namespaces

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GET_INSTRINFO_CTOR_DTOR

Enumeration Type Documentation

◆ ARMExeDomain

Function Documentation

◆ adjustDefLatency()

◆ canFoldIntoMOVCC()

◆ duplicateCPV()

◆ getBundledDefMI()

◆ getBundledUseMI()

◆ getCmpToAddCondition()

◆ getCorrespondingDRegAndLane()

◆ getImplicitSPRUseForDPRUse()

◆ getNumMicroOpsSingleIssuePlusExtras()

◆ getNumMicroOpsSwiftLdSt()

◆ getSwappedCondition()

◆ isEligibleForITBlock()

◆ isOptimizeCompareCandidate()

◆ isRedundantFlagInstr()

◆ isSuitableForMask()

Variable Documentation

◆ AddSubFlagsOpcodeMap

◆ ARM_MLxTable

◆ EnableARM3Addr