PPCISelDAGToDAG.cpp File Reference

#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <new>
#include <tuple>
#include <utility>
#include "PPCGenDAGISel.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "ppc-codegen"

Enumerations
enum	ICmpInGPRType {   ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64,   ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32,   ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64 }

Functions
	STATISTIC (NumSextSetcc, "Number of (sext(setcc)) nodes expanded into GPR sequence.")
	STATISTIC (NumZextSetcc, "Number of (zext(setcc)) nodes expanded into GPR sequence.")
	STATISTIC (SignExtensionsAdded, "Number of sign extensions for compare inputs added.")
	STATISTIC (ZeroExtensionsAdded, "Number of zero extensions for compare inputs added.")
	STATISTIC (NumLogicOpsOnComparison, "Number of logical ops on i1 values calculated in GPR.")
	STATISTIC (OmittedForNonExtendUses, "Number of compares not eliminated as they have non-extending uses.")
	STATISTIC (NumP9Setb, "Number of compares lowered to setb.")
static bool	isInt32Immediate (SDNode *N, unsigned &Imm)
	isInt32Immediate - This method tests to see if the node is a 32-bit constant operand. More...
static bool	isInt64Immediate (SDNode *N, uint64_t &Imm)
	isInt64Immediate - This method tests to see if the node is a 64-bit constant operand. More...
static bool	isInt32Immediate (SDValue N, unsigned &Imm)
static bool	isInt64Immediate (SDValue N, uint64_t &Imm)
	isInt64Immediate - This method tests to see if the value is a 64-bit constant operand. More...
static unsigned	getBranchHint (unsigned PCC, FunctionLoweringInfo *FuncInfo, const SDValue &DestMBB)
static bool	isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
static unsigned	selectI64ImmInstrCountDirect (int64_t Imm)
static uint64_t	Rot64 (uint64_t Imm, unsigned R)
static unsigned	selectI64ImmInstrCount (int64_t Imm)
static SDNode *	selectI64ImmDirect (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm)
static SDNode *	selectI64Imm (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm)
static unsigned	allUsesTruncate (SelectionDAG *CurDAG, SDNode *N)
static SDNode *	selectI64Imm (SelectionDAG *CurDAG, SDNode *N)
static PPC::Predicate	getPredicateForSetCC (ISD::CondCode CC)
static unsigned	getCRIdxForSetCC (ISD::CondCode CC, bool &Invert)
	getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted. More...
static unsigned int	getVCmpInst (MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate)
static bool	mayUseP9Setb (SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG, bool &NeedSwapOps, bool &IsUnCmp)
static bool	PeepholePPC64ZExtGather (SDValue Op32, SmallPtrSetImpl< SDNode *> &ToPromote)

Variables
cl::opt< bool >	ANDIGlueBug ("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
static cl::opt< bool >	UseBitPermRewriter ("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
static cl::opt< bool >	BPermRewriterNoMasking ("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden)
static cl::opt< bool >	EnableBranchHint ("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
static cl::opt< bool >	EnableTLSOpt ("ppc-tls-opt", cl::init(true), cl::desc("Enable tls optimization peephole"), cl::Hidden)
static cl::opt< ICmpInGPRType >	CmpInGPR ("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result.")))

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "ppc-codegen"

Definition at line 70 of file PPCISelDAGToDAG.cpp.

Enumeration Type Documentation

ICmpInGPRType

enum ICmpInGPRType

Enumerator
ICGPR_All
ICGPR_None
ICGPR_I32
ICGPR_I64
ICGPR_NonExtIn
ICGPR_Zext
ICGPR_Sext
ICGPR_ZextI32
ICGPR_SextI32
ICGPR_ZextI64
ICGPR_SextI64

Definition at line 111 of file PPCISelDAGToDAG.cpp.

Function Documentation

allUsesTruncate()

static unsigned allUsesTruncate ( SelectionDAG *  CurDAG, SDNode *  N  )

static

Definition at line 1004 of file PPCISelDAGToDAG.cpp.

References llvm::MemSDNode::getMemoryVT(), llvm::Use::getOperandNo(), llvm::EVT::getSizeInBits(), llvm::max(), llvm::ISD::STORE, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by selectI64Imm().

getBranchHint()

static unsigned getBranchHint ( unsigned  PCC, FunctionLoweringInfo *  FuncInfo, const SDValue &  DestMBB  )

static

Definition at line 487 of file PPCISelDAGToDAG.cpp.

References assert(), llvm::FunctionLoweringInfo::BPI, llvm::PPC::BR_NO_HINT, llvm::PPC::BR_NONTAKEN_HINT, llvm::PPC::BR_TAKEN_HINT, llvm::dbgs(), llvm::FunctionLoweringInfo::Fn, llvm::MachineBasicBlock::getBasicBlock(), llvm::BranchProbabilityInfo::getEdgeProbability(), llvm::Value::getName(), llvm::Instruction::getNumSuccessors(), llvm::Instruction::getSuccessor(), llvm::BasicBlock::getTerminator(), LLVM_DEBUG, llvm::max(), llvm::FunctionLoweringInfo::MBB, std::swap(), and Threshold.

Referenced by mayUseP9Setb().

getCRIdxForSetCC()

static unsigned getCRIdxForSetCC ( ISD::CondCode  CC, bool &  Invert  )

static

getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.

That is, lt = 0; ge = 0 inverted.

Definition at line 3838 of file PPCISelDAGToDAG.cpp.

References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

Referenced by getVCmpInst(), and mayUseP9Setb().

getPredicateForSetCC()

static PPC::Predicate getPredicateForSetCC ( ISD::CondCode  CC )

static

Definition at line 3807 of file PPCISelDAGToDAG.cpp.

References llvm_unreachable, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::PPC::PRED_NU, llvm::PPC::PRED_UN, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

Referenced by mayUseP9Setb().

getVCmpInst()

static unsigned int getVCmpInst ( MVT  VecVT, ISD::CondCode  CC, bool  HasVSX, bool &  Swap, bool &  Negate  )

static

Definition at line 3870 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::EVT::changeVectorElementTypeToInteger(), llvm::ISD::CopyFromReg, llvm::dyn_cast(), getCRIdxForSetCC(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::Glue, llvm::PPCSubtarget::hasQPX(), llvm::PPCSubtarget::hasSPE(), llvm::PPCSubtarget::hasVSX(), llvm::MVT::i32, llvm::MVT::i64, llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), isInt32Immediate(), llvm::isIntS16Immediate(), llvm::EVT::isVector(), llvm_unreachable, llvm::PPCISD::MFOCRF, N, llvm::AArch64ISD::NEG, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, std::swap(), T, llvm::PPCSubtarget::useCRBits(), llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MipsISD::VNOR.

isInt32Immediate() [1/2]

static bool isInt32Immediate ( SDNode *  N, unsigned &  Imm  )

static

isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.

If so Imm will receive the 32-bit value.

Definition at line 457 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i32, and N.

Referenced by getVCmpInst(), isInt32Immediate(), isOpcWithIntImmediate(), mayUseP9Setb(), and selectI64Imm().

isInt32Immediate() [2/2]

static bool isInt32Immediate ( SDValue  N, unsigned &  Imm  )

static

Definition at line 477 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getNode(), and isInt32Immediate().

isInt64Immediate() [1/2]

static bool isInt64Immediate ( SDNode *  N, uint64_t &  Imm  )

static

isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 467 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i64, and N.

Referenced by isInt64Immediate(), mayUseP9Setb(), and selectI64Imm().

isInt64Immediate() [2/2]

static bool isInt64Immediate ( SDValue  N, uint64_t &  Imm  )

static

isInt64Immediate - This method tests to see if the value is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 483 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getNode(), and isInt64Immediate().

isOpcWithIntImmediate()

static bool isOpcWithIntImmediate ( SDNode *  N, unsigned  Opc, unsigned &  Imm  )

static

Definition at line 540 of file PPCISelDAGToDAG.cpp.

References llvm::PPCISD::ADD_TLS, llvm::ISD::AND, llvm::LoadSDNode::getBasePtr(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::LoadSDNode::getOffset(), llvm::StoreSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), llvm::APInt::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, isInt32Immediate(), llvm::isRunOfOnes(), llvm::SDValue::isUndef(), llvm::ARM_MB::LD, llvm::BitmaskEnumDetail::Mask(), N, llvm::KnownBits::One, llvm::ISD::ROTL, llvm::ISD::SHL, llvm::MVT::SimpleTy, llvm::ISD::SRL, llvm::ARM_MB::ST, std::swap(), and llvm::KnownBits::Zero.

Referenced by mayUseP9Setb().

mayUseP9Setb()

static bool mayUseP9Setb ( SDNode *  N, const ISD::CondCode &  CC, SelectionDAG *  DAG, bool &  NeedSwapOps, bool &  IsUnCmp  )

static

Definition at line 4179 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, ANDIGlueBug, llvm::PPCISD::ANDIo_1_EQ_BIT, llvm::PPCISD::ANDIo_1_GT_BIT, llvm::ISD::ANY_EXTEND, assert(), llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::tgtok::Bits, llvm::ISD::BR_CC, llvm::ISD::BRIND, C, llvm::PPCISD::CALL, llvm::PPCISD::CMPB, llvm::PPCISD::COND_BRANCH, llvm::ISD::Constant, llvm::countTrailingOnes(), llvm::dbgs(), llvm::SDNode::dump(), llvm::dyn_cast(), llvm::SmallVectorBase::empty(), EnableBranchHint, EnableTLSOpt, llvm::SmallVectorTemplateCommon< T >::end(), llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FrameIndex, llvm::LSBaseSDNode::getAddressingMode(), llvm::LoadSDNode::getBasePtr(), getBranchHint(), llvm::MemSDNode::getChain(), llvm::TargetMachine::getCodeModel(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getConstantOperandVal(), getCRIdxForSetCC(), llvm::LoadSDNode::getExtensionType(), llvm::MachineFunction::getFunction(), llvm::APInt::getHighBitsSet(), llvm::SDNode::getMachineOpcode(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::LoadSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::GlobalValue::getParent(), llvm::Module::getPICLevel(), getPredicateForSetCC(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::APInt::getZExtValue(), llvm::PPCISD::GlobalBaseReg, llvm::MVT::Glue, llvm::PPCSubtarget::hasCMPB(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::PPCSubtarget::hasP8Vector(), llvm::PPCSubtarget::hasQPX(), llvm::PPCSubtarget::hasSPE(), llvm::PPCSubtarget::hasVSX(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86II::Imm64, llvm::PPCSubtarget::isELFv2ABI(), isInt32Immediate(), isInt64Immediate(), llvm::isInt< 16 >(), llvm::isIntS16Immediate(), llvm::PPCSubtarget::isISA3_0(), llvm::PPCSubtarget::isLittleEndian(), llvm::SDNode::isMachineOpcode(), llvm::isMask_64(), llvm::ConstantSDNode::isNullValue(), isOpcWithIntImmediate(), llvm::TargetMachine::isPositionIndependent(), llvm::PPCSubtarget::isPPC64(), llvm::isRunOfOnes(), llvm::PPCSubtarget::isSecurePlt(), llvm::ISD::isSignedIntSetCC(), llvm::PPCSubtarget::isSVR4ABI(), llvm::PPCSubtarget::isTargetELF(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::CodeModel::Large, LLVM_DEBUG, LLVM_FALLTHROUGH, llvm_unreachable, llvm::MipsISD::Lo, llvm::ISD::LOAD, llvm::BitmaskEnumDetail::Mask(), llvm::CodeModel::Medium, llvm::PPCISD::MFOCRF, llvm::PPCII::MO_PLT, llvm::PPCISD::MTCTR, N, llvm::CodeGenOpt::None, llvm::RISCVFenceField::O, llvm::SDNode::ops(), llvm::ISD::OR, llvm::MVT::Other, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::PPCISD::PPC32_PICGOT, llvm::ISD::PRE_INC, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::PPCISD::READ_TIME_BASE, llvm::ISD::ROTL, llvm::ISD::SCALAR_TO_VECTOR, llvm::MCID::Select, llvm::ISD::SELECT_CC, selectI64Imm(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::SDNode::setNodeId(), llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::PICLevel::SmallPIC, llvm::PPCISD::SRA_ADDZE, llvm::ISD::SRL, llvm::ISD::STORE, std::swap(), llvm::ISD::TargetConstant, llvm::ISD::TargetGlobalAddress, llvm::PPCISD::TOC_ENTRY, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_empty(), llvm::SDNode::use_end(), llvm::PPCSubtarget::useCRBits(), llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::PPCISD::VADD_SPLAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, llvm::PPCISD::XXPERMDI, llvm::KnownBits::Zero, and llvm::ISD::ZERO_EXTEND.

PeepholePPC64ZExtGather()

static bool PeepholePPC64ZExtGather ( SDValue  Op32, SmallPtrSetImpl< SDNode *> &  ToPromote  )

static

Definition at line 5980 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::AND, B, llvm::SmallPtrSetImpl< PtrType >::begin(), C, llvm::HexagonISD::CP, llvm::dbgs(), llvm::SDNode::dump(), llvm::SmallPtrSetImpl< PtrType >::end(), llvm::GlobalValue::getAlignment(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getMachineOpcode(), llvm::SDNode::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getVTList(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::PPCSubtarget::isDarwin(), llvm::isInt< 16 >(), llvm::SDValue::isMachineOpcode(), llvm::SDNode::isMachineOpcode(), llvm::PPCSubtarget::isPPC64(), llvm::ARM_MB::LD, LLVM_DEBUG, LLVM_FALLTHROUGH, llvm_unreachable, llvm::PPCII::MO_DTPREL_LO, llvm::PPCII::MO_TLSLD_LO, llvm::PPCII::MO_TOC_LO, llvm::SDVTList::NumVTs, llvm::SDNode::ops(), OR, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SDNode::use_empty(), llvm::SDNode::uses(), and llvm::SDVTList::VTs.

Rot64()

static uint64_t Rot64 ( uint64_t  Imm, unsigned  R  )

static

Definition at line 825 of file PPCISelDAGToDAG.cpp.

Referenced by selectI64Imm(), and selectI64ImmInstrCount().

selectI64Imm() [1/2]

static SDNode* selectI64Imm ( SelectionDAG *  CurDAG, const SDLoc &  dl, int64_t  Imm  )

static

Definition at line 944 of file PPCISelDAGToDAG.cpp.

References llvm::findLastSet(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::i64, llvm::AArch64CC::LS, Rot64(), selectI64ImmDirect(), and selectI64ImmInstrCountDirect().

Referenced by mayUseP9Setb(), and selectI64Imm().

selectI64Imm() [2/2]

static SDNode* selectI64Imm ( SelectionDAG *  CurDAG, SDNode *  N  )

static

Definition at line 1061 of file PPCISelDAGToDAG.cpp.

References llvm::MCID::Add, allUsesTruncate(), llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::tgtok::Bits, BPermRewriterNoMasking, CmpInGPR, llvm::MCID::Compare, llvm::dbgs(), llvm::SDNode::dump(), llvm::dyn_cast(), E, llvm::MipsISD::Ext, F(), llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getMachineOpcode(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::TargetLoweringBase::getPointerTy(), llvm::PPCInstrInfo::getRecordFormOpcode(), llvm::SDValue::getResNo(), llvm::ISD::getSetCCInverse(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::Glue, llvm::SDValue::hasOneUse(), llvm::PPCSubtarget::hasSPE(), llvm::PPCSubtarget::hasVSX(), I, llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, ICGPR_I32, ICGPR_I64, ICGPR_None, ICGPR_NonExtIn, ICGPR_Sext, ICGPR_SextI32, ICGPR_Zext, ICGPR_ZextI32, ICGPR_ZextI64, llvm::ARM_PROC::IE, INT64_MAX, llvm::isBitwiseNot(), isInt32Immediate(), isInt64Immediate(), llvm::isInt< 16 >(), llvm::isIntS16Immediate(), llvm::ConstantSDNode::isNullValue(), llvm::PPCTargetMachine::isPPC64(), llvm::isUInt< 16 >(), llvm::isUInt< 32 >(), llvm::ISD::isUnsignedIntSetCC(), isZero(), llvm::ISD::isZEXTLoad(), Kind, LLVM_DEBUG, LLVM_FALLTHROUGH, llvm_unreachable, llvm::ISD::LOAD, llvm::BitmaskEnumDetail::Mask(), llvm::max(), N, llvm::AArch64ISD::NEG, llvm::CodeGenOpt::None, llvm::operator<(), OR, llvm::ISD::OR, Other, llvm::remove_if(), llvm::SmallVectorImpl< T >::resize(), llvm::NVPTX::PTXCvtMode::RN, llvm::ISD::ROTL, llvm::PPCISD::SC, second, llvm::MCID::Select, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, selectI64Imm(), selectI64ImmInstrCount(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::SignExtend64(), llvm::sort(), llvm::ISD::SRL, std::swap(), llvm::ISD::TRUNCATE, UseBitPermRewriter, llvm::SDNode::uses(), llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

selectI64ImmDirect()

static SDNode* selectI64ImmDirect ( SelectionDAG *  CurDAG, const SDLoc &  dl, int64_t  Imm  )

static

Definition at line 859 of file PPCISelDAGToDAG.cpp.

References llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::isInt< 16 >(), llvm::isInt< 32 >(), llvm::MipsISD::Lo, and llvm::SignExtend64().

Referenced by selectI64Imm().

selectI64ImmInstrCount()

static unsigned selectI64ImmInstrCount ( int64_t  Imm )

static

Definition at line 829 of file PPCISelDAGToDAG.cpp.

References llvm::findLastSet(), llvm::AArch64CC::LS, Rot64(), and selectI64ImmInstrCountDirect().

Referenced by selectI64Imm().

selectI64ImmInstrCountDirect()

static unsigned selectI64ImmInstrCountDirect ( int64_t  Imm )

static

Definition at line 761 of file PPCISelDAGToDAG.cpp.

References llvm::isInt< 16 >(), llvm::isInt< 32 >(), and llvm::MipsISD::Lo.

Referenced by selectI64Imm(), and selectI64ImmInstrCount().

STATISTIC() [1/7]

STATISTIC	(	NumSextSetcc	,
		"Number of (sext(setcc)) nodes expanded into GPR sequence."
	)

STATISTIC() [2/7]

STATISTIC	(	NumZextSetcc	,
		"Number of (zext(setcc)) nodes expanded into GPR sequence."
	)

STATISTIC() [3/7]

STATISTIC	(	SignExtensionsAdded	,
		"Number of sign extensions for compare inputs added."
	)

STATISTIC() [4/7]

STATISTIC	(	ZeroExtensionsAdded	,
		"Number of zero extensions for compare inputs added."
	)

STATISTIC() [5/7]

STATISTIC	(	NumLogicOpsOnComparison	,
		"Number of logical ops on i1 values calculated in GPR."
	)

STATISTIC() [6/7]

STATISTIC	(	OmittedForNonExtendUses	,
		"Number of compares not eliminated as they have non-extending uses."
	)

STATISTIC() [7/7]

STATISTIC	(	NumP9Setb	,
		"Number of compares lowered to setb."
	)

Variable Documentation

ANDIGlueBug

cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)

Referenced by mayUseP9Setb().

BPermRewriterNoMasking

cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden)

static

Referenced by selectI64Imm().

CmpInGPR

cl::opt<ICmpInGPRType> CmpInGPR("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result.")))

static

Referenced by selectI64Imm().

EnableBranchHint

cl::opt<bool> EnableBranchHint("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)

static

Referenced by mayUseP9Setb().

EnableTLSOpt

cl::opt<bool> EnableTLSOpt("ppc-tls-opt", cl::init(true), cl::desc("Enable tls optimization peephole"), cl::Hidden)

static

Referenced by mayUseP9Setb().

UseBitPermRewriter

cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)

static

Referenced by selectI64Imm().