19 #include <type_traits> 23 static_assert(std::is_pod<MCSchedModel>::value,
24 "We shouldn't have a static constructor here");
26 DefaultMicroOpBufferSize,
27 DefaultLoopMicroOpBufferSize,
30 DefaultMispredictPenalty,
45 DefIdx != DefEnd; ++DefIdx) {
58 unsigned SchedClass)
const {
70 const MCInst &Inst)
const {
71 unsigned SchedClass = MCII.
get(Inst.
getOpcode()).getSchedClass();
99 double Temp = NumUnits * 1.0 / I->
Cycles;
100 Throughput = Throughput ? std::min(Throughput.
getValue(), Temp) : Temp;
113 const MCInst &Inst)
const {
114 unsigned SchedClass = MCII.
get(Inst.
getOpcode()).getSchedClass();
140 for (; I !=
E; ++
I) {
144 Throughput = Throughput ? std::min(Throughput.
getValue(), Temp) : Temp;
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents lattice values for constants.
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
unsigned getUnits() const
Returns the choice of FUs.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
unsigned getProcessorID() const
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
const T & getValue() const LLVM_LVALUE_FUNCTION
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Interface to description of machine instruction set.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const unsigned DefaultIssueWidth
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Specify the latency in cpu cycles for a particular scheduling class and def index.
static const MCSchedModel Default
unsigned getCycles() const
Returns the number of cycles the stage is occupied.
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
These values represent a non-pipelined step in the execution of an instruction.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
const InstrStage * endStage(unsigned ItinClassIndx) const
Return the last+1 stage of the itinerary.
Generic base class for all target subtargets.
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
uint16_t NumWriteLatencyEntries
unsigned getOpcode() const
Machine model for scheduling, bundling, and heuristics.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.