39 #define DEBUG_TYPE "mips-isel" 61 processFunctionAfterISel(MF);
83 bool MipsDAGToDAGISel::selectAddrDefault(
SDValue Addr,
SDValue &Base,
95 bool MipsDAGToDAGISel::selectIntAddr11MM(
SDValue Addr,
SDValue &Base,
101 bool MipsDAGToDAGISel::selectIntAddr12MM(
SDValue Addr,
SDValue &Base,
107 bool MipsDAGToDAGISel::selectIntAddr16MM(
SDValue Addr,
SDValue &Base,
113 bool MipsDAGToDAGISel::selectIntAddrLSL2MM(
SDValue Addr,
SDValue &Base,
119 bool MipsDAGToDAGISel::selectIntAddrSImm10(
SDValue Addr,
SDValue &Base,
125 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(
SDValue Addr,
SDValue &Base,
131 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(
SDValue Addr,
SDValue &Base,
137 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(
SDValue Addr,
SDValue &Base,
149 bool MipsDAGToDAGISel::selectAddr16SP(
SDValue Addr,
SDValue &Base,
155 bool MipsDAGToDAGISel::selectVSplat(
SDNode *
N,
APInt &Imm,
156 unsigned MinSizeInBits)
const {
161 bool MipsDAGToDAGISel::selectVSplatUimm1(
SDValue N,
SDValue &Imm)
const {
166 bool MipsDAGToDAGISel::selectVSplatUimm2(
SDValue N,
SDValue &Imm)
const {
171 bool MipsDAGToDAGISel::selectVSplatUimm3(
SDValue N,
SDValue &Imm)
const {
176 bool MipsDAGToDAGISel::selectVSplatUimm4(
SDValue N,
SDValue &Imm)
const {
181 bool MipsDAGToDAGISel::selectVSplatUimm5(
SDValue N,
SDValue &Imm)
const {
186 bool MipsDAGToDAGISel::selectVSplatUimm6(
SDValue N,
SDValue &Imm)
const {
191 bool MipsDAGToDAGISel::selectVSplatUimm8(
SDValue N,
SDValue &Imm)
const {
196 bool MipsDAGToDAGISel::selectVSplatSimm5(
SDValue N,
SDValue &Imm)
const {
201 bool MipsDAGToDAGISel::selectVSplatUimmPow2(
SDValue N,
SDValue &Imm)
const {
206 bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(
SDValue N,
SDValue &Imm)
const {
211 bool MipsDAGToDAGISel::selectVSplatMaskL(
SDValue N,
SDValue &Imm)
const {
216 bool MipsDAGToDAGISel::selectVSplatMaskR(
SDValue N,
SDValue &Imm)
const {
223 void MipsDAGToDAGISel::Select(
SDNode *Node) {
249 cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
251 "Unexpected unaligned loads/stores.");
260 bool MipsDAGToDAGISel::
261 SelectInlineAsmMemoryOperand(
const SDValue &
Op,
unsigned ConstraintID,
262 std::vector<SDValue> &OutOps) {
264 switch(ConstraintID) {
271 OutOps.push_back(Op);
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents lattice values for constants.
void setNodeId(int Id)
Set unique node id.
SDNode * getNode() const
get the SDNode which holds the desired result
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
static uint32_t getAlignment(const MCSectionCOFF &Sec)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const DataLayout & getDataLayout() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Represent the analysis usage information of a pass.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void dump() const
Dump this node, for debugging.
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
SDNode * getGlobalBaseReg()
getGlobalBaseReg - Output the instructions required to put the GOT address into a register...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
const TargetLowering * getTargetLowering() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getRegister(unsigned Reg, EVT VT)
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...