LLVM  8.0.1
Public Member Functions | List of all members
llvm::AArch64RegisterBankInfo Class Referencefinal

This class provides the information for the target register banks. More...

#include "Target/AArch64/AArch64RegisterBankInfo.h"

Inheritance diagram for llvm::AArch64RegisterBankInfo:
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Collaboration diagram for llvm::AArch64RegisterBankInfo:
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Public Member Functions

 AArch64RegisterBankInfo (const TargetRegisterInfo &TRI)
 
unsigned copyCost (const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
 Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B. More...
 
const RegisterBankgetRegBankFromRegClass (const TargetRegisterClass &RC) const override
 Get a register bank that covers RC. More...
 
InstructionMappings getInstrAlternativeMappings (const MachineInstr &MI) const override
 Get the alternative mappings for MI. More...
 
const InstructionMappinggetInstrMapping (const MachineInstr &MI) const override
 Get the mapping of the different operands of MI on the register bank. More...
 
- Public Member Functions inherited from llvm::RegisterBankInfo
const RegisterBankgetRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
 Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any. More...
 
virtual ~RegisterBankInfo ()=default
 
const RegisterBankgetRegBank (unsigned ID) const
 Get the register bank identified by ID. More...
 
const RegisterBankgetRegBank (unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the register bank of Reg. More...
 
unsigned getNumRegBanks () const
 Get the total number of register banks. More...
 
const InstructionMappinggetInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
 Method to get a uniquely generated InstructionMapping. More...
 
const InstructionMappinggetInvalidInstructionMapping () const
 Method to get a uniquely generated invalid InstructionMapping. More...
 

Additional Inherited Members

- Public Types inherited from llvm::RegisterBankInfo
using InstructionMappings = SmallVector< const InstructionMapping *, 4 >
 Convenient type to represent the alternatives for mapping an instruction. More...
 
- Static Public Member Functions inherited from llvm::RegisterBankInfo
static void applyDefaultMapping (const OperandsMapper &OpdMapper)
 Helper method to apply something that is like the default mapping. More...
 
static const TargetRegisterClassconstrainGenericRegister (unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
 Constrain the (possibly generic) virtual register Reg to RC. More...
 
- Public Attributes inherited from llvm::RegisterBankInfo
struct llvm::RegisterBankInfo::PartialMapping ScalarAddx2
 
 VectorAdd
 Get the possible mapping for MI. More...
 
- Static Public Attributes inherited from llvm::RegisterBankInfo
static const unsigned DefaultMappingID = UINT_MAX
 Identifier used when the related instruction mapping instance is generated by target independent code. More...
 
static const unsigned InvalidMappingID = UINT_MAX - 1
 Identifier used when the related instruction mapping instance is generated by the default constructor. More...
 
- Protected Types inherited from llvm::AArch64GenRegisterBankInfo
enum  PartialMappingIdx {
  PMI_None = -1, PMI_FPR16 = 1, PMI_FPR32, PMI_FPR64,
  PMI_FPR128, PMI_FPR256, PMI_FPR512, PMI_GPR32,
  PMI_GPR64, PMI_FirstGPR = PMI_GPR32, PMI_LastGPR = PMI_GPR64, PMI_FirstFPR = PMI_FPR16,
  PMI_LastFPR = PMI_FPR512, PMI_Min = PMI_FirstFPR
}
 
enum  ValueMappingIdx {
  InvalidIdx = 0, First3OpsIdx = 1, Last3OpsIdx = 22, DistanceBetweenRegBanks = 3,
  FirstCrossRegCpyIdx = 25, LastCrossRegCpyIdx = 39, DistanceBetweenCrossRegCpy = 2, FPExt16To32Idx = 41,
  FPExt16To64Idx = 43, FPExt32To64Idx = 45, FPExt64To128Idx = 47
}
 
- Protected Member Functions inherited from llvm::RegisterBankInfo
 RegisterBankInfo (RegisterBank **RegBanks, unsigned NumRegBanks)
 Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. More...
 
 RegisterBankInfo ()
 This constructor is meaningless. More...
 
RegisterBankgetRegBank (unsigned ID)
 Get the register bank identified by ID. More...
 
const TargetRegisterClassgetMinimalPhysRegClass (unsigned Reg, const TargetRegisterInfo &TRI) const
 Get the MinimalPhysRegClass for Reg. More...
 
const InstructionMappinggetInstrMappingImpl (const MachineInstr &MI) const
 Try to get the mapping of MI. More...
 
const PartialMappinggetPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 Get the uniquely generated PartialMapping for the given arguments. More...
 
const ValueMappinggetValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 The most common ValueMapping consists of a single PartialMapping. More...
 
const ValueMappinggetValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
 Get the ValueMapping for the given arguments. More...
 
template<typename Iterator >
const ValueMappinggetOperandsMapping (Iterator Begin, Iterator End) const
 Get the uniquely generated array of ValueMapping for the elements of between Begin and End. More...
 
const ValueMappinggetOperandsMapping (const SmallVectorImpl< const ValueMapping *> &OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the elements of OpdsMapping. More...
 
const ValueMappinggetOperandsMapping (std::initializer_list< const ValueMapping *> OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the given arguments. More...
 
- Static Protected Member Functions inherited from llvm::AArch64GenRegisterBankInfo
static bool checkPartialMap (unsigned Idx, unsigned ValStartIdx, unsigned ValLength, const RegisterBank &RB)
 
static bool checkValueMapImpl (unsigned Idx, unsigned FirstInBank, unsigned Size, unsigned Offset)
 
static bool checkPartialMappingIdx (PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
 
static unsigned getRegBankBaseIdxOffset (unsigned RBIdx, unsigned Size)
 
static const RegisterBankInfo::ValueMappinggetValueMapping (PartialMappingIdx RBIdx, unsigned Size)
 Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size. More...
 
static const RegisterBankInfo::ValueMappinggetCopyMapping (unsigned DstBankID, unsigned SrcBankID, unsigned Size)
 Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register bank to the DstBankID register bank with a size of Size. More...
 
static const RegisterBankInfo::ValueMappinggetFPExtMapping (unsigned DstSize, unsigned SrcSize)
 Get the instruction mapping for G_FPEXT. More...
 
- Protected Attributes inherited from llvm::RegisterBankInfo
RegisterBank ** RegBanks
 Hold the set of supported register banks. More...
 
unsigned NumRegBanks
 Total number of register banks. More...
 
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
 Keep dynamically allocated PartialMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
 Keep dynamically allocated ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
 Keep dynamically allocated array of ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
 Keep dynamically allocated InstructionMapping in a separate map. More...
 
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
 Getting the minimal register class of a physreg is expensive. More...
 
- Static Protected Attributes inherited from llvm::AArch64GenRegisterBankInfo
static RegisterBankInfo::PartialMapping PartMappings []
 
static RegisterBankInfo::ValueMapping ValMappings []
 
static PartialMappingIdx BankIDToCopyMapIdx []
 

Detailed Description

This class provides the information for the target register banks.

Definition at line 103 of file AArch64RegisterBankInfo.h.

Constructor & Destructor Documentation

◆ AArch64RegisterBankInfo()

AArch64RegisterBankInfo::AArch64RegisterBankInfo ( const TargetRegisterInfo TRI)

Member Function Documentation

◆ copyCost()

unsigned AArch64RegisterBankInfo::copyCost ( const RegisterBank A,
const RegisterBank B,
unsigned  Size 
) const
overridevirtual

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Since register banks may cover different size, Size specifies what will be the size in bits that will be copied around.

Note
Since this is a copy, both registers have the same size.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 205 of file AArch64RegisterBankInfo.cpp.

References llvm::RegisterBankInfo::copyCost().

Referenced by getInstrAlternativeMappings(), and getInstrMapping().

◆ getInstrAlternativeMappings()

RegisterBankInfo::InstructionMappings AArch64RegisterBankInfo::getInstrAlternativeMappings ( const MachineInstr MI) const
overridevirtual

◆ getInstrMapping()

const RegisterBankInfo::InstructionMapping & AArch64RegisterBankInfo::getInstrMapping ( const MachineInstr MI) const
overridevirtual

Get the mapping of the different operands of MI on the register bank.

This mapping should be the direct translation of MI. In other words, when MI is mapped with the returned mapping, only the register banks of the operands of MI need to be updated. In particular, neither the opcode nor the type of MI needs to be updated for this direct mapping.

The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.

For instance, if MI is a vector add, the mapping should not be a scalarization of the add.

Postcondition
returnedVal.verify(MI).
Note
If returnedVal does not verify MI, this would probably mean that the target does not support that instruction.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 442 of file AArch64RegisterBankInfo.cpp.

References assert(), copyCost(), llvm::RegisterBankInfo::DefaultMappingID, DefMI, llvm::AArch64GenRegisterBankInfo::getCopyMapping(), llvm::AArch64GenRegisterBankInfo::getFPExtMapping(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getInvalidInstructionMapping(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::LLT::getSizeInBits(), llvm::getSizeInBits(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getType(), llvm::AArch64GenRegisterBankInfo::getValueMapping(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isPHI(), llvm::TargetRegisterInfo::isPhysicalRegister(), isPreISelGenericFloatingPointOpcode(), llvm::isPreISelGenericOpcode(), llvm::MachineOperand::isReg(), llvm::LLT::isValid(), llvm::RegisterBankInfo::InstructionMapping::isValid(), llvm::LLT::isVector(), LLVM_FALLTHROUGH, MRI, llvm::AArch64GenRegisterBankInfo::PartMappings, llvm::AArch64GenRegisterBankInfo::PMI_FirstFPR, llvm::AArch64GenRegisterBankInfo::PMI_FirstGPR, llvm::AArch64GenRegisterBankInfo::PMI_None, Size, TRI, llvm::MachineRegisterInfo::use_instructions(), and UseMI.

◆ getRegBankFromRegClass()

const RegisterBank & AArch64RegisterBankInfo::getRegBankFromRegClass ( const TargetRegisterClass RC) const
overridevirtual

Get a register bank that covers RC.

Precondition
RC is a user-defined register class (as opposed as one generated by TableGen).
Note
The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.
Todo:
This should be TableGen'ed.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 226 of file AArch64RegisterBankInfo.cpp.

References llvm::TargetRegisterClass::getID(), llvm::RegisterBankInfo::getRegBank(), and llvm_unreachable.


The documentation for this class was generated from the following files: