13 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H 14 #define LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H 26 class MachineBasicBlock;
27 class MachineDominanceFrontier;
28 class MachineDominatorTree;
29 class MachineRegisterInfo;
30 class TargetRegisterInfo;
42 return Map.emplace(B, Empty).first->second;
47 std::map<MachineBasicBlock*,RegisterAggr> Map;
50 using NodeRef = std::pair<NodeId, LaneBitmask>;
53 using RefMap = std::map<RegisterId, NodeRefSet>;
56 : DFG(g),
TRI(g.getTRI()), PRI(g.getPRI()), MDT(g.getDT()),
57 MDF(g.getDF()), LiveMap(g.getPRI()), Empty(), NoRegs(g.getPRI()) {}
60 bool TopShadows,
bool FullChain,
const RegisterAggr &DefRRs);
88 auto F = RealUseMap.find(P);
89 return F == RealUseMap.end() ? Empty :
F->second;
122 std::map<NodeId, RefMap> RealUseMap;
125 std::map<MachineBasicBlock*,std::set<MachineBasicBlock*>> IIDF;
128 std::map<MachineBasicBlock*,RefMap> PhiLON;
135 std::map<MachineBasicBlock*,RefMap> PhiLOX;
141 std::pair<NodeSet,bool> getAllReachingDefsRecImpl(
RegisterRef RefRR,
143 unsigned Nest,
unsigned MaxNest);
150 #endif // LLVM_LIB_TARGET_HEXAGON_RDFLIVENESS_H const LiveMapType & getLiveMap() const
A common definition of LaneBitmask for use in TableGen and CodeGen.
This class represents lattice values for constants.
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr< RefNode *> RefA)
std::pair< NodeSet, bool > getAllReachingDefsRec(RegisterRef RefRR, NodeAddr< RefNode *> RefA, NodeSet &Visited, const NodeSet &Defs)
unsigned const TargetRegisterInfo * TRI
NodeAddr< RefNode * > getNearestAliasedRef(RegisterRef RefRR, NodeAddr< InstrNode *> IA)
Find the nearest ref node aliased to RefRR, going upwards in the data flow, starting from the instruc...
LiveMapType(const PhysicalRegisterInfo &pri)
RegisterAggr & operator[](MachineBasicBlock *B)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr< DefNode *> DefA)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr< RefNode *> RefA, bool TopShadows, bool FullChain, const RegisterAggr &DefRRs)
const RefMap & getRealUses(NodeId P) const
std::pair< NodeId, LaneBitmask > NodeRef
LiveMapType & getLiveMap()
std::map< RegisterId, NodeRefSet > RefMap
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
std::set< NodeId > NodeSet
NodeList getAllReachingDefs(NodeAddr< RefNode *> RefA)
std::set< NodeRef > NodeRefSet
NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr< DefNode *> DefA, const RegisterAggr &DefRRs)
Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...