14 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H 15 #define LLVM_CODEGEN_TARGETPASSCONFIG_H 24 class LLVMTargetMachine;
25 struct MachineSchedContext;
27 class ScheduleDAGInstrs;
57 bool IsInstance =
false;
68 assert(!IsInstance &&
"Not a Pass ID");
73 assert(IsInstance &&
"Not a Pass Instance");
79 static const bool value =
true;
94 unsigned StartBeforeInstanceNum = 0;
95 unsigned StartBeforeCount = 0;
97 unsigned StartAfterInstanceNum = 0;
98 unsigned StartAfterCount = 0;
100 unsigned StopBeforeInstanceNum = 0;
101 unsigned StopBeforeCount = 0;
103 unsigned StopAfterInstanceNum = 0;
104 unsigned StopAfterCount = 0;
107 bool Stopped =
false;
108 bool AddingMachinePasses =
false;
120 void setStartStopPasses();
125 bool Initialized =
false;
129 bool DisableVerify =
false;
132 bool EnableTailMerge =
true;
136 bool RequireCodeGenSCCOrder =
false;
140 bool addCoreISelPasses();
152 template<
typename TMC> TMC &
getTM()
const {
153 return *
static_cast<TMC*
>(
TM);
163 static bool hasLimitedCodeGenPipeline();
167 static bool willCompleteCodeGenPipeline();
173 getLimitedCodeGenPipelineReason(
const char *Separator =
"/")
const;
182 setOpt(RequireCodeGenSCCOrder,
Enable);
192 bool VerifyAfter =
true,
bool PrintAfter =
true);
208 bool isPassSubstitutedOrOverridden(
AnalysisID ID)
const;
211 bool getOptimizeRegAlloc()
const;
215 bool usingDefaultRegAlloc()
const;
222 bool addISelPasses();
226 virtual void addIRPasses();
229 void addPassesToHandleExceptions();
233 virtual void addCodeGenPrepare();
237 virtual void addISelPrepare();
278 virtual void addMachinePasses();
303 void printAndVerify(
const std::string &Banner);
306 void addPrintPass(
const std::string &Banner);
310 void addVerifyPass(
const std::string &Banner);
315 bool isGlobalISelAbortEnabled()
const;
320 virtual bool reportDiagnosticWhenGlobalISelFallback()
const;
324 void setOpt(
bool &Opt,
bool Val);
341 virtual void addMachineSSAOptimization();
359 virtual FunctionPass *createTargetRegisterAllocator(
bool Optimized);
363 virtual void addFastRegAlloc(
FunctionPass *RegAllocPass);
367 virtual void addOptimizedRegAlloc(
FunctionPass *RegAllocPass);
386 virtual void addMachineLateOptimization();
395 virtual bool addGCPasses();
398 virtual void addBlockPlacement();
421 bool printAfter =
true);
430 void addPass(
Pass *
P,
bool verifyAfter =
true,
bool printAfter =
true);
439 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H Pass interface - Implemented by all 'passes'.
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
This class represents lattice values for constants.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
void setDisableVerify(bool Disable)
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
bool requiresCodeGenSCCOrder() const
TMC & getTM() const
Get the right type of TargetMachine for this target.
block Block Frequency true
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
IdentifyingPassPtr(Pass *InstancePtr)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Target-Independent Code Generator Pass Configuration Options.
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
bool getEnableTailMerge() const
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
void setEnableTailMerge(bool Enable)
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
void pm(uint64_t &Value)
Adjusts a program memory address.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
isPodLike - This is a type trait that is used to determine whether a given type can be copied around ...
ImmutablePass class - This class is used to provide information that does not need to be run...
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
A ScheduleDAG for scheduling lists of MachineInstr.
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Pass * getInstance() const
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IdentifyingPassPtr(AnalysisID IDPtr)
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...