LLVM  8.0.1
ARMHazardRecognizer.h
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1 //===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines hazard recognizers for scheduling ARM functions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
15 #define LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
16 
18 
19 namespace llvm {
20 
21 class ARMBaseInstrInfo;
22 class ARMBaseRegisterInfo;
23 class ARMSubtarget;
24 class MachineInstr;
25 
26 /// ARMHazardRecognizer handles special constraints that are not expressed in
27 /// the scheduling itinerary. This is only used during postRA scheduling. The
28 /// ARM preRA scheduler uses an unspecialized instance of the
29 /// ScoreboardHazardRecognizer.
31  MachineInstr *LastMI;
32  unsigned FpMLxStalls;
33 
34 public:
36  const ScheduleDAG *DAG)
37  : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"),
38  LastMI(nullptr) {}
39 
40  HazardType getHazardType(SUnit *SU, int Stalls) override;
41  void Reset() override;
42  void EmitInstruction(SUnit *SU) override;
43  void AdvanceCycle() override;
44  void RecedeCycle() override;
45 };
46 
47 } // end namespace llvm
48 
49 #endif
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
This class represents lattice values for constants.
Definition: AllocatorList.h:24
Itinerary data supplied by a subtarget to be used by a target.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
ARMHazardRecognizer(const InstrItineraryData *ItinData, const ScheduleDAG *DAG)
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
Representation of each machine instruction.
Definition: MachineInstr.h:64
ARMHazardRecognizer handles special constraints that are not expressed in the scheduling itinerary...
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:246
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...