RISCVISelLowering.cpp File Reference

#include "RISCVISelLowering.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"

Include dependency graph for RISCVISelLowering.cpp:

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "riscv-lower"

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static void	normaliseSetCC (SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
static unsigned	getBranchOpcodeForIntCondCode (ISD::CondCode CC)
static bool	isVariableShift (SDValue Val)
static bool	isVariableSDivUDivURem (SDValue Val)
static MachineBasicBlock *	emitSplitF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
static MachineBasicBlock *	emitBuildPairF64Pseudo (MachineInstr &MI, MachineBasicBlock *BB)
static bool	CC_RISCVAssign2XLen (unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
static bool	CC_RISCV (const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
static SDValue	convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackF64OnRV32DSoftABI (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static Intrinsic::ID	getIntrinsicForMaskedAtomicRMWBinOp32 (AtomicRMWInst::BinOp BinOp)

Variables
static const MCPhysReg	ArgGPRs []

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-lower"

Definition at line 38 of file RISCVISelLowering.cpp.

Function Documentation

CC_RISCV()

static bool CC_RISCV ( const DataLayout &  DL, unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State, bool  IsFixed, bool  IsRet, Type *  OrigTy  )

static

Definition at line 802 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::array_lengthof(), assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), llvm::dbgs(), llvm::SmallVectorBase::empty(), llvm::MVT::f32, llvm::MVT::f64, llvm::CCValAssign::Full, llvm::MachineFunction::getDataLayout(), llvm::CCState::getFirstUnallocated(), llvm::MachineFunction::getFunction(), llvm::Function::getFunctionType(), llvm::DataLayout::getLargestLegalIntTypeSizeInBits(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getOrigAlign(), llvm::FunctionType::getParamType(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::FunctionType::getReturnType(), llvm::DataLayout::getTypeAllocSize(), llvm::MVT::i32, llvm::MVT::i64, llvm::CCValAssign::Indirect, llvm::MipsISD::Ins, llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), LLVM_DEBUG, llvm_unreachable, llvm::SmallVectorTemplateBase< T >::push_back(), Reg, and llvm::SmallVectorBase::size().

Referenced by unpackF64OnRV32DSoftABI().

CC_RISCVAssign2XLen()

static bool CC_RISCVAssign2XLen ( unsigned  XLen, CCState &  State, CCValAssign  VA1, ISD::ArgFlagsTy  ArgFlags1, unsigned  ValNo2, MVT  ValVT2, MVT  LocVT2, ISD::ArgFlagsTy  ArgFlags2  )

static

Definition at line 765 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), llvm::CCValAssign::getValVT(), llvm::max(), and Reg.

Referenced by CC_RISCV().

convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 974 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), and llvm_unreachable.

Referenced by unpackF64OnRV32DSoftABI(), and unpackFromRegLoc().

convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 1007 of file RISCVISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), and llvm_unreachable.

Referenced by unpackF64OnRV32DSoftABI().

emitBuildPairF64Pseudo()

static MachineBasicBlock* emitBuildPairF64Pseudo ( MachineInstr &  MI, MachineBasicBlock *  BB  )

static

Definition at line 625 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::TargetInstrInfo::loadRegFromStackSlot(), llvm::MachineMemOperand::MOStore, and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

emitSplitF64Pseudo()

static MachineBasicBlock* emitSplitF64Pseudo ( MachineInstr &  MI, MachineBasicBlock *  BB  )

static

Definition at line 594 of file RISCVISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::MachineMemOperand::MOLoad, llvm::TargetInstrInfo::storeRegToStackSlot(), and TII.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

getBranchOpcodeForIntCondCode()

static unsigned getBranchOpcodeForIntCondCode ( ISD::CondCode  CC )

static

Definition at line 299 of file RISCVISelLowering.cpp.

References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.

Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().

getIntrinsicForMaskedAtomicRMWBinOp32()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp32 ( AtomicRMWInst::BinOp  BinOp )

static

Definition at line 1731 of file RISCVISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::IRBuilder< T, Inserter >::CreateSub(), llvm::AtomicCmpXchgInst::getCompareOperand(), llvm::Module::getDataLayout(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::getInt32(), llvm::Instruction::getModule(), llvm::AtomicRMWInst::getOperation(), llvm::AtomicRMWInst::getOrdering(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::DataLayout::getTypeStoreSizeInBits(), llvm::AtomicRMWInst::getValOperand(), llvm::RISCVSubtarget::getXLen(), llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), llvm::TargetLoweringBase::MaskedIntrinsic, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::TargetLoweringBase::None, llvm::Intrinsic::riscv_masked_atomicrmw_add_i32, llvm::Intrinsic::riscv_masked_atomicrmw_max_i32, llvm::Intrinsic::riscv_masked_atomicrmw_min_i32, llvm::Intrinsic::riscv_masked_atomicrmw_nand_i32, llvm::Intrinsic::riscv_masked_atomicrmw_sub_i32, llvm::Intrinsic::riscv_masked_atomicrmw_umax_i32, llvm::Intrinsic::riscv_masked_atomicrmw_umin_i32, llvm::Intrinsic::riscv_masked_atomicrmw_xchg_i32, llvm::Intrinsic::riscv_masked_cmpxchg_i32, Size, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

isVariableSDivUDivURem()

static bool isVariableSDivUDivURem ( SDValue  Val )

static

Definition at line 530 of file RISCVISelLowering.cpp.

References llvm::ISD::Constant, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::SDIV, llvm::ISD::UDIV, and llvm::ISD::UREM.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

isVariableShift()

static bool isVariableShift ( SDValue  Val )

static

Definition at line 517 of file RISCVISelLowering.cpp.

References llvm::ISD::Constant, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().

normaliseSetCC()

static void normaliseSetCC ( SDValue &  LHS, SDValue &  RHS, ISD::CondCode &  CC  )

static

Definition at line 282 of file RISCVISelLowering.cpp.

References llvm::ISD::getSetCCSwappedOperands(), llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and std::swap().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

unpackF64OnRV32DSoftABI()

static SDValue unpackF64OnRV32DSoftABI ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 1052 of file RISCVISelLowering.cpp.

References llvm::ISD::ADD, llvm::MachineRegisterInfo::addLiveIn(), llvm::Address, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, Arg, llvm::Function::arg_empty(), ArgGPRs, assert(), llvm::RISCVISD::BuildPairF64, llvm::CallingConv::C, llvm::RISCVISD::CALL, Callee, CC_RISCV(), Context, convertLocVTToValVT(), convertValVTToLocVT(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::CreateStackObject(), llvm::SelectionDAG::CreateStackTemporary(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SmallVectorBase::empty(), llvm::MVT::f64, false, llvm::CallingConv::Fast, llvm::CCValAssign::Full, G, llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::RISCVRegisterInfo::getCallPreservedMask(), llvm::TargetRegisterInfo::getCallPreservedMask(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getCALLSEQ_START(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getDataLayout(), llvm::CCState::getFirstUnallocated(), llvm::MachinePointerInfo::getFixedStack(), llvm::Function::getFnAttribute(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemcpy(), llvm::CCState::getNextStackOffset(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::Function::getReturnType(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValue(), llvm::Attribute::getValueAsString(), llvm::CCValAssign::getValVT(), llvm::SelectionDAG::getVTList(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::Glue, llvm::GlobalValue::hasExternalWeakLinkage(), llvm::Function::hasFnAttribute(), llvm::MipsISD::Hi, I, llvm::MVT::i32, llvm::CCValAssign::Indirect, llvm::ISD::ArgFlagsTy::isByVal(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm::Type::isVoidTy(), Kind, llvm::MipsISD::Lo, llvm::makeArrayRef(), llvm::BitmaskEnumDetail::Mask(), llvm::RISCVISD::MRET_FLAG, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), Reg, llvm::report_fatal_error(), llvm::RISCVISD::RET_FLAG, llvm::MachineFrameInfo::setHasTailCall(), llvm::RISCVMachineFunctionInfo::setVarArgsFrameIndex(), llvm::RISCVMachineFunctionInfo::setVarArgsSaveSize(), Size, llvm::SmallVectorBase::size(), llvm::ArrayRef< T >::size(), llvm::RISCVISD::SplitF64, llvm::RISCVISD::SRET_FLAG, llvm::SPII::Store, llvm::RISCVISD::TAIL, llvm::ISD::TokenFactor, TRI, unpackFromMemLoc(), unpackFromRegLoc(), and llvm::RISCVISD::URET_FLAG.

unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 1025 of file RISCVISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getSizeInBits(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

Referenced by unpackF64OnRV32DSoftABI().

unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 990 of file RISCVISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), convertLocVTToValVT(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getRegInfo(), and llvm::CCValAssign::Indirect.

Referenced by unpackF64OnRV32DSoftABI().

Variable Documentation

ArgGPRs

const MCPhysReg ArgGPRs[]

static

Initial value:

= {
  RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
  RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
}

Definition at line 758 of file RISCVISelLowering.cpp.

Referenced by CC_RISCV(), CC_RISCVAssign2XLen(), isSortedByValueNo(), and unpackF64OnRV32DSoftABI().