17 #ifndef LLVM_CODEGEN_LIVEINTERVALUNION_H 18 #define LLVM_CODEGEN_LIVEINTERVALUNION_H 30 class TargetRegisterInfo;
34 template <
unsigned Element>
class SparseBitVector;
85 unsigned getTag()
const {
return Tag; }
115 bool CheckedFirstInterference =
false;
116 bool SeenAllInterferences =
false;
118 unsigned UserTag = 0;
120 void reset(
unsigned NewUserTag,
const LiveRange &NewLR,
122 LiveUnion = &NewLiveUnion;
124 InterferingVRegs.
clear();
125 CheckedFirstInterference =
false;
126 SeenAllInterferences =
false;
127 Tag = NewLiveUnion.
getTag();
128 UserTag = NewUserTag;
134 LiveUnion(&LIU), LR(&LR) {}
140 if (UserTag == NewUserTag && LR == &NewLR && LiveUnion == &NewLiveUnion &&
145 reset(NewUserTag, NewLR, NewLiveUnion);
164 return InterferingVRegs;
186 assert(idx < Size &&
"idx out of bounds");
191 assert(Idx < Size &&
"Idx out of bounds");
199 #endif // LLVM_CODEGEN_LIVEINTERVALUNION_H
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
LiveIntervalUnion(Allocator &a)
This class represents lattice values for constants.
LiveInterval - This class represents the liveness of a register, or stack slot.
ConstSegmentIter end() const
unsigned const TargetRegisterInfo * TRI
friend class const_iterator
const_iterator begin() const
This class represents the liveness of a register, stack slot, etc.
const Map & getMap() const
Query interferences between a single live virtual register and a live interval union.
Query(const LiveRange &LR, const LiveIntervalUnion &LIU)
Query & operator=(const Query &)=delete
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
KeyT start() const
start - Return the smallest mapped key in a non-empty map.
const SmallVectorImpl< LiveInterval * > & interferingVRegs() const
void init(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)
void clear()
clear - Remove all entries.
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end()...
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())
bool changedSince(unsigned tag) const
changedSince - Return true if the union change since getTag returned tag.
typename Sizer::Allocator Allocator
SegmentIter find(SlotIndex x)
const_iterator end() const
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
SlotIndex startIndex() const
unsigned getTag() const
getTag - Return an opaque tag representing the current state of the union.
LiveSegments::Allocator Allocator
LiveIntervalUnion & operator[](unsigned idx)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
ConstSegmentIter find(SlotIndex x) const
void unify(LiveInterval &VirtReg, const LiveRange &Range)
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
Segments::const_iterator const_iterator
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool seenAllInterferences() const
bool empty() const
empty - Return true when no intervals are mapped.
ConstSegmentIter begin() const
void verify(LiveVirtRegBitSet &VisitedVRegs)
void extract(LiveInterval &VirtReg, const LiveRange &Range)
bool isSeenInterference(LiveInterval *VirtReg) const
NDEBUG.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
const LiveIntervalUnion & operator[](unsigned Idx) const
SlotIndex - An opaque wrapper around machine indexes.