27 #define DEBUG_TYPE "regalloc" 40 while (SegPos.
valid()) {
41 SegPos.
insert(RegPos->start, RegPos->end, &VirtReg);
42 if (++RegPos == RegEnd)
51 SegPos.
insert(RegEnd->start, RegEnd->end, &VirtReg);
52 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
53 SegPos.
insert(RegPos->start, RegPos->end, &VirtReg);
68 assert(SegPos.
value() == &VirtReg &&
"Inconsistent LiveInterval");
89 OS <<
" [" <<
SI.start() <<
' ' <<
SI.stop() <<
"):" 99 VisitedVRegs.
set(
SI.value()->reg);
121 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
122 return InterferingVRegs.size();
125 if (!CheckedFirstInterference) {
126 CheckedFirstInterference =
true;
129 if (LR->empty() || LiveUnion->empty()) {
130 SeenAllInterferences =
true;
136 LiveUnionI.setMap(LiveUnion->getMap());
137 LiveUnionI.find(LRI->start);
142 while (LiveUnionI.valid()) {
143 assert(LRI != LREnd &&
"Reached end of LR");
146 while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
149 if (VReg != RecentReg && !isSeenInterference(VReg)) {
151 InterferingVRegs.push_back(VReg);
152 if (InterferingVRegs.size() >= MaxInterferingRegs)
153 return InterferingVRegs.
size();
156 if (!(++LiveUnionI).valid()) {
157 SeenAllInterferences =
true;
158 return InterferingVRegs.size();
164 assert(LRI->end <= LiveUnionI.start() &&
"Expected non-overlap");
167 LRI = LR->advanceTo(LRI, LiveUnionI.start());
172 if (LRI->start < LiveUnionI.stop())
176 LiveUnionI.advanceTo(LRI->start);
178 SeenAllInterferences =
true;
179 return InterferingVRegs.size();
191 for (
unsigned i = 0; i !=
Size; ++i)
198 for (
unsigned i = 0; i !=
Size; ++i)
LiveIntervalUnion(Allocator &a)
This class represents lattice values for constants.
LiveInterval - This class represents the liveness of a register, or stack slot.
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
unsigned const TargetRegisterInfo * TRI
bool valid() const
valid - Return true if the current position is valid, false for end().
const_iterator begin() const
This class represents the liveness of a register, stack slot, etc.
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void advanceTo(KeyT x)
advanceTo - Move to the first interval with stop >= x, or end().
void erase()
erase - Erase the current interval.
const_iterator find(KeyT x) const
find - Return an iterator pointing to the first interval ending at or after x, or end()...
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())
const KeyT & start() const
start - Return the beginning of the current interval.
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
LiveSegments::Allocator Allocator
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_malloc(size_t Sz)
void unify(LiveInterval &VirtReg, const LiveRange &Range)
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
Segments::const_iterator const_iterator
void init(LiveIntervalUnion::Allocator &, unsigned Size)
const ValT & value() const
value - Return the mapped value at the current interval.
void insert(KeyT a, KeyT b, ValT y)
insert - Insert mapping [a;b] -> y before the current position.
void verify(LiveVirtRegBitSet &VisitedVRegs)
void extract(LiveInterval &VirtReg, const LiveRange &Range)
bool isSeenInterference(LiveInterval *VirtReg) const
NDEBUG.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.