ARMLoadStoreOptimizer.cpp File Reference

#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMISelLowering.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstddef>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <utility>

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "arm-ldst-opt"
#define	ARM_LOAD_STORE_OPT_NAME   "ARM load / store optimization pass"
#define	ARM_PREALLOC_LOAD_STORE_OPT_NAME   "ARM pre- register allocation load / store optimization pass"

Functions
	STATISTIC (NumLDMGened, "Number of ldm instructions generated")
	STATISTIC (NumSTMGened, "Number of stm instructions generated")
	STATISTIC (NumVLDMGened, "Number of vldm instructions generated")
	STATISTIC (NumVSTMGened, "Number of vstm instructions generated")
	STATISTIC (NumLdStMoved, "Number of load / store instructions moved")
	STATISTIC (NumLDRDFormed,"Number of ldrd created before allocation")
	STATISTIC (NumSTRDFormed,"Number of strd created before allocation")
	STATISTIC (NumLDRD2LDM, "Number of ldrd instructions turned back into ldm")
	STATISTIC (NumSTRD2STM, "Number of strd instructions turned back into stm")
	STATISTIC (NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's")
	STATISTIC (NumSTRD2STR, "Number of strd instructions turned back into str's")
	INITIALIZE_PASS (ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false, false) static bool definesCPSR(const MachineInstr &MI)
static int	getMemoryOpOffset (const MachineInstr &MI)
static const MachineOperand &	getLoadStoreBaseOp (const MachineInstr &MI)
static const MachineOperand &	getLoadStoreRegOp (const MachineInstr &MI)
static int	getLoadStoreMultipleOpcode (unsigned Opcode, ARM_AM::AMSubMode Mode)
static ARM_AM::AMSubMode	getLoadStoreMultipleSubMode (unsigned Opcode)
static bool	isT1i32Load (unsigned Opc)
static bool	isT2i32Load (unsigned Opc)
static bool	isi32Load (unsigned Opc)
static bool	isT1i32Store (unsigned Opc)
static bool	isT2i32Store (unsigned Opc)
static bool	isi32Store (unsigned Opc)
static bool	isLoadSingle (unsigned Opc)
static unsigned	getImmScale (unsigned Opc)
static unsigned	getLSMultipleTransferSize (const MachineInstr *MI)
static bool	ContainsReg (const ArrayRef< std::pair< unsigned, bool >> &Regs, unsigned Reg)
static bool	isValidLSDoubleOffset (int Offset)
static bool	mayCombineMisaligned (const TargetSubtargetInfo &STI, const MachineInstr &MI)
	Return true for loads/stores that can be combined to a double/multi operation without increasing the requirements for alignment. More...
static unsigned	getUpdatingLSMultipleOpcode (unsigned Opc, ARM_AM::AMSubMode Mode)
static int	isIncrementOrDecrement (const MachineInstr &MI, unsigned Reg, ARMCC::CondCodes Pred, unsigned PredReg)
	Check if the given instruction increments or decrements a register and return the amount it is incremented/decremented. More...
static MachineBasicBlock::iterator	findIncDecBefore (MachineBasicBlock::iterator MBBI, unsigned Reg, ARMCC::CondCodes Pred, unsigned PredReg, int &Offset)
	Searches for an increment or decrement of Reg before MBBI. More...
static MachineBasicBlock::iterator	findIncDecAfter (MachineBasicBlock::iterator MBBI, unsigned Reg, ARMCC::CondCodes Pred, unsigned PredReg, int &Offset)
	Searches for a increment or decrement of Reg after MBBI. More...
static unsigned	getPreIndexedLoadStoreOpcode (unsigned Opc, ARM_AM::AddrOpc Mode)
static unsigned	getPostIndexedLoadStoreOpcode (unsigned Opc, ARM_AM::AddrOpc Mode)
static bool	isMemoryOp (const MachineInstr &MI)
	Returns true if instruction is a memory operation that this pass is capable of operating on. More...
static void	InsertLDR_STR (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII)
	INITIALIZE_PASS (ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt", ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) bool ARMPreAllocLoadStoreOpt
static bool	IsSafeAndProfitableToMove (bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSetImpl< MachineInstr *> &MemOps, SmallSet< unsigned, 4 > &MemRegs, const TargetRegisterInfo *TRI, AliasAnalysis *AA)

Variables
static cl::opt< bool >	AssumeMisalignedLoadStores ("arm-assume-misaligned-load-store", cl::Hidden, cl::init(false), cl::desc("Be more conservative in ARM load/store opt"))
	This switch disables formation of double/multi instructions that could potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP disabled. More...

Macro Definition Documentation

ARM_LOAD_STORE_OPT_NAME

#define ARM_LOAD_STORE_OPT_NAME   "ARM load / store optimization pass"

Definition at line 94 of file ARMLoadStoreOptimizer.cpp.

ARM_PREALLOC_LOAD_STORE_OPT_NAME

#define ARM_PREALLOC_LOAD_STORE_OPT_NAME   "ARM pre- register allocation load / store optimization pass"

Definition at line 1999 of file ARMLoadStoreOptimizer.cpp.

DEBUG_TYPE

#define DEBUG_TYPE   "arm-ldst-opt"

Definition at line 71 of file ARMLoadStoreOptimizer.cpp.

Function Documentation

ContainsReg()

static bool ContainsReg ( const ArrayRef< std::pair< unsigned, bool >> &  Regs, unsigned  Reg  )

static

Definition at line 611 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::condCodeOp(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::RegState::Define, llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::erase(), first, llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineInstrBuilder::getInstr(), llvm::getInstrPredicate(), llvm::getKillRegState(), getLoadStoreBaseOp(), getLoadStoreMultipleOpcode(), getLoadStoreRegOp(), getMemoryOpOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::ia, llvm::ARM_AM::ib, llvm::MachineInstr::implicit_operands(), llvm::RegState::ImplicitDefine, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::is_contained(), llvm::isARMLowRegister(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), isi32Load(), isi32Store(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isKill(), isLoadSingle(), llvm::MachineOperand::isReg(), llvm::MachineInstr::killsRegister(), llvm::MachineBasicBlock::LQR_Dead, llvm::make_range(), MI, Mode, llvm::predOps(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MachineInstr::readsRegister(), Reg, second, llvm::t1CondCodeOp(), TII, TRI, and llvm::MachineInstr::uses().

findIncDecAfter()

static MachineBasicBlock::iterator findIncDecAfter ( MachineBasicBlock::iterator  MBBI, unsigned  Reg, ARMCC::CondCodes  Pred, unsigned  PredReg, int &  Offset  )

static

Searches for a increment or decrement of Reg after MBBI.

Definition at line 1224 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), findIncDecBefore(), llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineFunction::getFunction(), llvm::getInstrPredicate(), llvm::getKillRegState(), getLoadStoreMultipleSubMode(), getLSMultipleTransferSize(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getUpdatingLSMultipleOpcode(), llvm::ARM_AM::ia, llvm::ARM_AM::ib, isIncrementOrDecrement(), llvm::MachineOperand::isKill(), llvm::MachineInstr::memoperands(), MI, Mode, llvm::Function::optForMinSize(), llvm::MachineInstrBuilder::setMemRefs(), and TII.

Referenced by getPostIndexedLoadStoreOpcode().

findIncDecBefore()

static MachineBasicBlock::iterator findIncDecBefore ( MachineBasicBlock::iterator  MBBI, unsigned  Reg, ARMCC::CondCodes  Pred, unsigned  PredReg, int &  Offset  )

static

Searches for an increment or decrement of Reg before MBBI.

Definition at line 1204 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), and isIncrementOrDecrement().

Referenced by findIncDecAfter(), and getPostIndexedLoadStoreOpcode().

getImmScale()

static unsigned getImmScale ( unsigned  Opc )

static

Definition at line 418 of file ARMLoadStoreOptimizer.cpp.

References llvm_unreachable.

Referenced by getLSMultipleTransferSize().

getLoadStoreBaseOp()

static const MachineOperand& getLoadStoreBaseOp ( const MachineInstr &  MI )

static

Definition at line 243 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstr::getOperand().

Referenced by ContainsReg(), getPostIndexedLoadStoreOpcode(), InsertLDR_STR(), and mayCombineMisaligned().

getLoadStoreMultipleOpcode()

static int getLoadStoreMultipleOpcode ( unsigned  Opcode, ARM_AM::AMSubMode  Mode  )

static

Definition at line 251 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::ARM_AM::ia, llvm::ARM_AM::ib, and llvm_unreachable.

Referenced by ContainsReg(), and IsSafeAndProfitableToMove().

getLoadStoreMultipleSubMode()

static ARM_AM::AMSubMode getLoadStoreMultipleSubMode ( unsigned  Opcode )

static

Definition at line 336 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::ARM_AM::ia, llvm::ARM_AM::ib, and llvm_unreachable.

Referenced by findIncDecAfter().

getLoadStoreRegOp()

static const MachineOperand& getLoadStoreRegOp ( const MachineInstr &  MI )

static

Definition at line 247 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineInstr::getOperand().

Referenced by ContainsReg(), getLSMultipleTransferSize(), and mayCombineMisaligned().

getLSMultipleTransferSize()

static unsigned getLSMultipleTransferSize ( const MachineInstr *  MI )

static

Definition at line 435 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::add, assert(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), getImmScale(), getLoadStoreRegOp(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getReg(), Reg, llvm::MachineOperand::setImm(), llvm::MachineBasicBlock::succ_size(), llvm::t1CondCodeOp(), TII, and TRI.

Referenced by findIncDecAfter(), getPostIndexedLoadStoreOpcode(), IsSafeAndProfitableToMove(), and mayCombineMisaligned().

getMemoryOpOffset()

static int getMemoryOpOffset ( const MachineInstr &  MI )

static

Definition at line 215 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::ARM_AM::getAM5Offset(), llvm::ARM_AM::getAM5Op(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::ARM_AM::sub.

Referenced by ContainsReg(), InsertLDR_STR(), and IsSafeAndProfitableToMove().

getPostIndexedLoadStoreOpcode()

static unsigned getPostIndexedLoadStoreOpcode ( unsigned  Opc, ARM_AM::AddrOpc  Mode  )

static

Definition at line 1351 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, llvm::MachineBasicBlock::erase(), findIncDecAfter(), findIncDecBefore(), llvm::ARM_AM::getAM2Opc(), llvm::ARM_AM::getAM5Offset(), llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getInstrPredicate(), llvm::getKillRegState(), getLoadStoreBaseOp(), getLSMultipleTransferSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), getPreIndexedLoadStoreOpcode(), llvm::MachineOperand::getReg(), llvm::MachineInstr::implicit_operands(), isi32Load(), isi32Store(), llvm::MachineOperand::isKill(), isLoadSingle(), llvm::RegState::Kill, llvm_unreachable, llvm::MachineInstr::memoperands(), llvm::ARM_AM::no_shift, llvm::predOps(), llvm::MachineInstrBuilder::setMemRefs(), llvm::ARM_AM::sub, and TII.

getPreIndexedLoadStoreOpcode()

static unsigned getPreIndexedLoadStoreOpcode ( unsigned  Opc, ARM_AM::AddrOpc  Mode  )

static

Definition at line 1326 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::add, and llvm_unreachable.

Referenced by getPostIndexedLoadStoreOpcode().

getUpdatingLSMultipleOpcode()

static unsigned getUpdatingLSMultipleOpcode ( unsigned  Opc, ARM_AM::AMSubMode  Mode  )

static

Definition at line 1104 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::ARM_AM::ia, llvm::ARM_AM::ib, and llvm_unreachable.

Referenced by findIncDecAfter().

INITIALIZE_PASS() [1/2]

INITIALIZE_PASS	(	ARMLoadStoreOpt	,
		"arm-ldst-opt"	,
		ARM_LOAD_STORE_OPT_NAME	,
		false	,
		false
	)		const &

Definition at line 199 of file ARMLoadStoreOptimizer.cpp.

INITIALIZE_PASS() [2/2]

INITIALIZE_PASS	(	ARMPreAllocLoadStoreOpt	,
		"arm-prera-ldst-opt"	,
		ARM_PREALLOC_LOAD_STORE_OPT_NAME	,
		false	,
		false
	)

Definition at line 2048 of file ARMLoadStoreOptimizer.cpp.

References AssumeMisalignedLoadStores, Modified, MRI, TII, and TRI.

InsertLDR_STR()

static void InsertLDR_STR ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator &  MBBI, int  Offset, bool  isDef, unsigned  NewOpc, unsigned  Reg, bool  RegDeadKill, bool  RegUndef, unsigned  BaseReg, bool  BaseKill, bool  BaseUndef, ARMCC::CondCodes  Pred, unsigned  PredReg, const TargetInstrInfo *  TII  )

static

Definition at line 1605 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, Allocator, assert(), llvm::MachineBasicBlock::begin(), llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::MachineInstr::copyImplicitOps(), E, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::MachineFunction::end(), llvm::MachineBasicBlock::erase(), llvm::MCInstrInfo::get(), llvm::MachineFrameInfo::getCalleeSavedInfo(), llvm::getDeadRegState(), llvm::getDefRegState(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::getInstrPredicate(), llvm::getKillRegState(), llvm::MachineBasicBlock::getLastNonDebugInstr(), getLoadStoreBaseOp(), getMemoryOpOffset(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::getTargetLowering(), llvm::getUndefRegState(), I, Info, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), isLoadSingle(), isMemoryOp(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, llvm_unreachable, MI, Modified, llvm::predOps(), Reg, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), llvm::sort(), TII, and TRI.

isi32Load()

static bool isi32Load ( unsigned  Opc )

static

Definition at line 398 of file ARMLoadStoreOptimizer.cpp.

References isT1i32Load(), and isT2i32Load().

Referenced by ContainsReg(), getPostIndexedLoadStoreOpcode(), isLoadSingle(), and mayCombineMisaligned().

isi32Store()

static bool isi32Store ( unsigned  Opc )

static

Definition at line 410 of file ARMLoadStoreOptimizer.cpp.

References isT1i32Store(), and isT2i32Store().

Referenced by ContainsReg(), getPostIndexedLoadStoreOpcode(), and mayCombineMisaligned().

isIncrementOrDecrement()

static int isIncrementOrDecrement ( const MachineInstr &  MI, unsigned  Reg, ARMCC::CondCodes  Pred, unsigned  PredReg  )

static

Check if the given instruction increments or decrements a register and return the amount it is incremented/decremented.

Returns 0 if the CPSR flags generated by the instruction are possibly read as well.

Definition at line 1174 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineOperand::getImm(), llvm::getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by findIncDecAfter(), and findIncDecBefore().

isLoadSingle()

static bool isLoadSingle ( unsigned  Opc )

static

Definition at line 414 of file ARMLoadStoreOptimizer.cpp.

References isi32Load().

Referenced by ContainsReg(), getPostIndexedLoadStoreOpcode(), InsertLDR_STR(), and IsSafeAndProfitableToMove().

isMemoryOp()

static bool isMemoryOp ( const MachineInstr &  MI )

static

Returns true if instruction is a memory operation that this pass is capable of operating on.

Definition at line 1552 of file ARMLoadStoreOptimizer.cpp.

References llvm::MachineMemOperand::getAlignment(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineMemOperand::isVolatile(), and llvm::MachineInstr::memoperands_begin().

Referenced by InsertLDR_STR(), and IsSafeAndProfitableToMove().

IsSafeAndProfitableToMove()

static bool IsSafeAndProfitableToMove ( bool  isLd, unsigned  Base, MachineBasicBlock::iterator  I, MachineBasicBlock::iterator  E, SmallPtrSetImpl< MachineInstr *> &  MemOps, SmallSet< unsigned, 4 > &  MemRegs, const TargetRegisterInfo *  TRI, AliasAnalysis *  AA  )

static

Definition at line 2070 of file ARMLoadStoreOptimizer.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::clear(), llvm::SmallVectorImpl< T >::clear(), llvm::MachineInstrBuilder::cloneMergedMemRefs(), llvm::SmallSet< T, N, C >::count(), llvm::SmallPtrSetImpl< PtrType >::count(), llvm::dbgs(), llvm::RegState::Define, E, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::find(), getAlignment(), llvm::ARM_AM::getAM3Opc(), llvm::Function::getContext(), llvm::MachineInstr::getDebugLoc(), llvm::getInstrPredicate(), llvm::Type::getInt64Ty(), getLoadStoreMultipleOpcode(), getLSMultipleTransferSize(), getMemoryOpOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getReg(), llvm::MachineInstr::hasOneMemOperand(), llvm::ARM_AM::ia, llvm::SmallSet< T, N, C >::insert(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isDebugInstr(), llvm::MachineOperand::isDef(), isLoadSingle(), isMemoryOp(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isTerminator(), isVolatile(), LLVM_DEBUG, llvm::MachineInstr::memoperands_begin(), MRI, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, llvm::ARMRI::RegPairEven, llvm::ARMRI::RegPairOdd, llvm::TargetRegisterInfo::regsOverlap(), llvm::SmallVectorBase::size(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::size(), llvm::SmallSet< T, N, C >::size(), llvm::sort(), llvm::MachineBasicBlock::splice(), llvm::ARM_AM::sub, TII, and TRI.

isT1i32Load()

static bool isT1i32Load ( unsigned  Opc )

static

Definition at line 390 of file ARMLoadStoreOptimizer.cpp.

Referenced by isi32Load().

isT1i32Store()

static bool isT1i32Store ( unsigned  Opc )

static

Definition at line 402 of file ARMLoadStoreOptimizer.cpp.

Referenced by isi32Store().

isT2i32Load()

static bool isT2i32Load ( unsigned  Opc )

static

Definition at line 394 of file ARMLoadStoreOptimizer.cpp.

Referenced by isi32Load().

isT2i32Store()

static bool isT2i32Store ( unsigned  Opc )

static

Definition at line 406 of file ARMLoadStoreOptimizer.cpp.

Referenced by isi32Store().

isValidLSDoubleOffset()

static bool isValidLSDoubleOffset ( int  Offset )

static

Definition at line 962 of file ARMLoadStoreOptimizer.cpp.

References llvm::abs().

Referenced by mayCombineMisaligned().

mayCombineMisaligned()

static bool mayCombineMisaligned ( const TargetSubtargetInfo &  STI, const MachineInstr &  MI  )

static

Return true for loads/stores that can be combined to a double/multi operation without increasing the requirements for alignment.

Definition at line 971 of file ARMLoadStoreOptimizer.cpp.

References Allocator, AssumeMisalignedLoadStores, C, llvm::TargetSubtargetInfo::getFrameLowering(), getLoadStoreBaseOp(), getLoadStoreRegOp(), getLSMultipleTransferSize(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getReg(), getReg(), llvm::TargetFrameLowering::getTransientStackAlignment(), I, isi32Load(), isi32Store(), llvm::MachineOperand::isUndef(), isValidLSDoubleOffset(), llvm::max(), MI, Reg, Size, and TRI.

STATISTIC() [1/11]

STATISTIC	(	NumLDMGened	,
		"Number of ldm instructions generated"
	)

STATISTIC() [2/11]

STATISTIC	(	NumSTMGened	,
		"Number of stm instructions generated"
	)

STATISTIC() [3/11]

STATISTIC	(	NumVLDMGened	,
		"Number of vldm instructions generated"
	)

STATISTIC() [4/11]

STATISTIC	(	NumVSTMGened	,
		"Number of vstm instructions generated"
	)

STATISTIC() [5/11]

STATISTIC	(	NumLdStMoved	,
		"Number of load / store instructions moved"
	)

STATISTIC() [6/11]

STATISTIC	(	NumLDRDFormed	,
		"Number of ldrd created before allocation"
	)

STATISTIC() [7/11]

STATISTIC	(	NumSTRDFormed	,
		"Number of strd created before allocation"
	)

STATISTIC() [8/11]

STATISTIC	(	NumLDRD2LDM	,
		"Number of ldrd instructions turned back into ldm"
	)

STATISTIC() [9/11]

STATISTIC	(	NumSTRD2STM	,
		"Number of strd instructions turned back into stm"
	)

STATISTIC() [10/11]

STATISTIC	(	NumLDRD2LDR	,
		"Number of ldrd instructions turned back into ldr's"
	)

STATISTIC() [11/11]

STATISTIC	(	NumSTRD2STR	,
		"Number of strd instructions turned back into str's"
	)

Variable Documentation

AssumeMisalignedLoadStores

cl::opt<bool> AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden, cl::init(false), cl::desc("Be more conservative in ARM load/store opt"))

static

This switch disables formation of double/multi instructions that could potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP disabled.

This can be used to create libraries that are robust even when users provoke undefined behaviour by supplying misaligned pointers.

See also

mayCombineMisaligned()

Referenced by INITIALIZE_PASS(), and mayCombineMisaligned().