ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs. More...

#include "CodeGen/SelectionDAG/ScheduleDAGSDNodes.h"

Inheritance diagram for llvm::ScheduleDAGSDNodes:

Collaboration diagram for llvm::ScheduleDAGSDNodes:

[legend]

Classes
class	RegDefIter
	RegDefIter - In place iteration over the values defined by an SUnit. More...

Public Member Functions
	ScheduleDAGSDNodes (MachineFunction &mf)

	~ScheduleDAGSDNodes () override=default

void	Run (SelectionDAG dag, MachineBasicBlock bb)
	Run - perform scheduling. More...

SUnit *	newSUnit (SDNode *N)
	NewSUnit - Creates a new SUnit and return a ptr to it. More...

SUnit *	Clone (SUnit *Old)
	Clone - Creates a clone of the specified SUnit. More...

void	BuildSchedGraph (AliasAnalysis *AA)
	BuildSchedGraph - Build the SUnit graph from the selection dag that we are input. More...

void	InitNumRegDefsLeft (SUnit *SU)
	InitNumRegDefsLeft - Determine the # of regs defined by this node. More...

virtual void	computeLatency (SUnit *SU)
	computeLatency - Compute node latency. More...

virtual void	computeOperandLatency (SDNode Def, SDNode Use, unsigned OpIdx, SDep &dep) const

virtual void	Schedule ()=0
	Schedule - Order nodes according to selected style, filling in the Sequence member. More...

void	VerifyScheduledSequence (bool isBottomUp)
	VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of scheduled instructions. More...

virtual MachineBasicBlock *	EmitSchedule (MachineBasicBlock::iterator &InsertPos)
	EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Sequence. More...

void	dumpNode (const SUnit &SU) const override

void	dump () const override

void	dumpSchedule () const

std::string	getGraphNodeLabel (const SUnit *SU) const override
	Returns a label for an SUnit node in a visualization of the ScheduleDAG. More...

std::string	getDAGName () const override
	Return the basic block label. More...

virtual void	getCustomGraphFeatures (GraphWriter< ScheduleDAG *> &GW) const

Public Member Functions inherited from llvm::ScheduleDAG
	ScheduleDAG (MachineFunction &mf)

virtual	~ScheduleDAG ()

void	clearDAG ()
	Clears the DAG state (between regions). More...

const MCInstrDesc *	getInstrDesc (const SUnit *SU) const
	Returns the MCInstrDesc of this SUnit. More...

virtual void	viewGraph (const Twine &Name, const Twine &Title)
	Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. More...

virtual void	viewGraph ()
	Out-of-line implementation with no arguments is handy for gdb. More...

void	dumpNodeName (const SUnit &SU) const

virtual void	addCustomGraphFeatures (GraphWriter< ScheduleDAG *> &) const
	Adds custom features for a visualization of the ScheduleDAG. More...

unsigned	VerifyScheduledDAG (bool isBottomUp)
	Verifies that all SUnits were scheduled and that their state is consistent. More...

Static Public Member Functions
static bool	isPassiveNode (SDNode *Node)
	isPassiveNode - Return true if the node is a non-scheduled leaf. More...

Public Attributes
MachineBasicBlock *	BB

SelectionDAG *	DAG

const InstrItineraryData *	InstrItins

std::vector< SUnit * >	Sequence
	The schedule. Null SUnit*'s represent noop instructions. More...

Public Attributes inherited from llvm::ScheduleDAG
const LLVMTargetMachine &	TM
	Target processor. More...

const TargetInstrInfo *	TII
	Target instruction information. More...

const TargetRegisterInfo *	TRI
	Target processor register info. More...

MachineFunction &	MF
	Machine function. More...

MachineRegisterInfo &	MRI
	Virtual/real register map. More...

std::vector< SUnit >	SUnits
	The scheduling units. More...

SUnit	EntrySU
	Special node for the region entry. More...

SUnit	ExitSU
	Special node for the region exit. More...

bool	StressSched

Protected Member Functions
virtual bool	forceUnitLatencies () const
	ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one. More...

Protected Member Functions inherited from llvm::ScheduleDAG
void	dumpNodeAll (const SUnit &SU) const

Detailed Description

ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.

Edges between SUnits are initially based on edges in the SelectionDAG, and additional edges can be added by the schedulers as heuristics. SDNodes such as Constants, Registers, and a few others that are not interesting to schedulers are not allocated SUnits.

SDNodes with MVT::Glue operands are grouped along with the flagged nodes into a single SUnit so that they are scheduled together.

SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output edges. Physical register dependence information is not carried in the DAG and must be handled explicitly by schedulers.

Definition at line 46 of file ScheduleDAGSDNodes.h.

Constructor & Destructor Documentation

◆ ScheduleDAGSDNodes()

ScheduleDAGSDNodes::ScheduleDAGSDNodes ( MachineFunction & mf )

explicit

Definition at line 49 of file ScheduleDAGSDNodes.cpp.

◆ ~ScheduleDAGSDNodes()

llvm::ScheduleDAGSDNodes::~ScheduleDAGSDNodes ( )

overridedefault

Member Function Documentation

◆ BuildSchedGraph()

void ScheduleDAGSDNodes::BuildSchedGraph ( AliasAnalysis * AA )

BuildSchedGraph - Build the SUnit graph from the selection dag that we are input.

This SUnit graph is similar to the SelectionDAG, but excludes nodes that aren't interesting to scheduling, and represents flagged together nodes with a single SUnit.

This SUnit graph is similar to the SelectionDAG, but excludes nodes that aren't interesting to scheduling, and represents glued together nodes with a single SUnit.

Definition at line 513 of file ScheduleDAGSDNodes.cpp.

References llvm::ISD::CopyFromReg, llvm::SDNode::getMachineOpcode(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::SDNode::isMachineOpcode(), and llvm::MVT::Other.

◆ Clone()

SUnit * ScheduleDAGSDNodes::Clone ( SUnit * Old )

Clone - Creates a clone of the specified SUnit.

It does not copy the predecessors / successors info nor the temporary scheduling states.

Definition at line 90 of file ScheduleDAGSDNodes.cpp.

References llvm::SUnit::getNode(), llvm::SUnit::hasPhysRegClobbers, llvm::SUnit::hasPhysRegDefs, llvm::SUnit::isCall, llvm::SUnit::isCallOp, llvm::SUnit::isCloned, llvm::SUnit::isCommutable, llvm::SUnit::isScheduleHigh, llvm::SUnit::isScheduleLow, llvm::SUnit::isTwoAddress, llvm::SUnit::isVRegCycle, llvm::SUnit::Latency, newSUnit(), llvm::SUnit::OrigNode, and llvm::SUnit::SchedulingPref.

◆ computeLatency()

void ScheduleDAGSDNodes::computeLatency ( SUnit * SU )

virtual

computeLatency - Compute node latency.

Definition at line 590 of file ScheduleDAGSDNodes.cpp.

References forceUnitLatencies(), llvm::SDNode::getGluedNode(), llvm::TargetInstrInfo::getInstrLatency(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), HighLatencyCycles, InstrItins, llvm::InstrItineraryData::isEmpty(), llvm::TargetInstrInfo::isHighLatencyDef(), llvm::SDNode::isMachineOpcode(), llvm::SUnit::Latency, N, llvm::ScheduleDAG::TII, and llvm::ISD::TokenFactor.

◆ computeOperandLatency()

void ScheduleDAGSDNodes::computeOperandLatency	(	SDNode *	Def,
		SDNode *	Use,
		unsigned	OpIdx,
		SDep &	dep
	)		const

virtual

◆ dump()

void ScheduleDAGSDNodes::dump ( ) const

overridevirtual

Implements llvm::ScheduleDAG.

Definition at line 675 of file ScheduleDAGSDNodes.cpp.

References llvm::ScheduleDAG::dumpNodeAll(), llvm::ScheduleDAG::EntrySU, llvm::ScheduleDAG::ExitSU, llvm::SUnit::getNode(), and llvm::ScheduleDAG::SUnits.

◆ dumpNode()

void ScheduleDAGSDNodes::dumpNode ( const SUnit & SU ) const

overridevirtual

Implements llvm::ScheduleDAG.

Definition at line 651 of file ScheduleDAGSDNodes.cpp.

References llvm::SmallVectorTemplateCommon< T >::back(), llvm::dbgs(), llvm::SDNode::dump(), llvm::ScheduleDAG::dumpNodeName(), llvm::SmallVectorBase::empty(), llvm::SDNode::getGluedNode(), llvm::SUnit::getNode(), N, llvm::SmallVectorTemplateBase< T >::pop_back(), and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by dumpSchedule().

◆ dumpSchedule()

void ScheduleDAGSDNodes::dumpSchedule ( ) const

Definition at line 687 of file ScheduleDAGSDNodes.cpp.

References llvm::dbgs(), dumpNode(), and Sequence.

◆ EmitSchedule()

MachineBasicBlock * ScheduleDAGSDNodes::EmitSchedule ( MachineBasicBlock::iterator & InsertPos )

virtual

EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Sequence.

EmitSchedule - Emit the machine code in scheduled order.

Return the new InsertPos and MachineBasicBlock that contains this insertion point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does not necessarily refer to returned BB. The emitter may split blocks.

Definition at line 810 of file ScheduleDAGSDNodes.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T >::back(), BB, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::MachineFunction::begin(), llvm::SelectionDAG::ByvalParmDbgBegin(), llvm::SelectionDAG::ByvalParmDbgEnd(), DAG, llvm::SelectionDAG::DbgBegin(), llvm::SelectionDAG::DbgEnd(), llvm::SelectionDAG::DbgLabelBegin(), llvm::SelectionDAG::DbgLabelEnd(), llvm::InstrEmitter::EmitDbgLabel(), llvm::InstrEmitter::EmitDbgValue(), llvm::InstrEmitter::EmitNode(), llvm::SmallVectorBase::empty(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::InstrEmitter::getBlock(), llvm::MachineBasicBlock::getFirstNonPHI(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::SDNode::getGluedNode(), llvm::InstrEmitter::getInsertPos(), llvm::SUnit::getNode(), llvm::SDDbgValue::getOrder(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::SelectionDAG::hasDebugValues(), llvm::MachineBasicBlock::insert(), llvm::TargetInstrInfo::insertNoop(), llvm::SUnit::isCloned, MI, N, llvm::SUnit::OrigNode, llvm::SmallVectorTemplateBase< T >::pop_back(), ProcessSourceNode(), llvm::SmallVectorTemplateBase< T >::push_back(), Sequence, llvm::SmallVectorBase::size(), and llvm::ScheduleDAG::TII.