23 #define DEBUG_TYPE "llvm-mca" 27 Listeners.insert(Listener);
28 for (
auto &S : Stages)
29 S->addListener(Listener);
32 bool Pipeline::hasWorkToProcess() {
33 return any_of(Stages, [](
const std::unique_ptr<Stage> &S) {
34 return S->hasWorkToComplete();
39 assert(!Stages.empty() &&
"Unexpected empty pipeline found!");
43 if (
Error Err = runCycle())
44 return std::move(Err);
47 }
while (hasWorkToProcess());
52 Error Pipeline::runCycle() {
55 for (
auto I = Stages.rbegin(),
E = Stages.rend();
I !=
E && !Err; ++
I) {
56 const std::unique_ptr<Stage> &S = *
I;
57 Err = S->cycleStart();
62 Stage &FirstStage = *Stages[0];
67 for (
auto I = Stages.rbegin(),
E = Stages.rend();
I !=
E && !Err; ++
I) {
68 const std::unique_ptr<Stage> &S = *
I;
76 assert(S &&
"Invalid null stage in input!");
77 if (!Stages.empty()) {
78 Stage *Last = Stages.back().get();
82 Stages.push_back(std::move(S));
85 void Pipeline::notifyCycleBegin() {
88 Listener->onCycleBegin();
91 void Pipeline::notifyCycleEnd() {
94 Listener->onCycleEnd();
void addEventListener(HWEventListener *Listener)
This class represents lattice values for constants.
virtual Error execute(InstRef &IR)=0
The primary action that this stage performs on instruction IR.
Subclass of Error for the sole purpose of identifying the success path in the type system...
An InstRef contains both a SourceMgr index and Instruction pair.
Tagged union holding either a T or a Error.
This file implements an ordered container of stages that simulate the pipeline of a hardware backend...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual bool isAvailable(const InstRef &IR) const
Returns true if it can execute IR during this cycle.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
This file defines the main interface for hardware event listeners.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Expected< unsigned > run()
Returns the total number of simulated cycles.
void appendStage(std::unique_ptr< Stage > S)
void setNextInSequence(Stage *NextStage)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Lightweight error class with error context and mandatory checking.
Statically lint checks LLVM IR