LLVM  8.0.1
Pipeline.cpp
Go to the documentation of this file.
1 //===--------------------- Pipeline.cpp -------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 ///
11 /// This file implements an ordered container of stages that simulate the
12 /// pipeline of a hardware backend.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/MCA/Pipeline.h"
18 #include "llvm/Support/Debug.h"
19 
20 namespace llvm {
21 namespace mca {
22 
23 #define DEBUG_TYPE "llvm-mca"
24 
26  if (Listener)
27  Listeners.insert(Listener);
28  for (auto &S : Stages)
29  S->addListener(Listener);
30 }
31 
32 bool Pipeline::hasWorkToProcess() {
33  return any_of(Stages, [](const std::unique_ptr<Stage> &S) {
34  return S->hasWorkToComplete();
35  });
36 }
37 
39  assert(!Stages.empty() && "Unexpected empty pipeline found!");
40 
41  do {
42  notifyCycleBegin();
43  if (Error Err = runCycle())
44  return std::move(Err);
45  notifyCycleEnd();
46  ++Cycles;
47  } while (hasWorkToProcess());
48 
49  return Cycles;
50 }
51 
52 Error Pipeline::runCycle() {
53  Error Err = ErrorSuccess();
54  // Update stages before we start processing new instructions.
55  for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) {
56  const std::unique_ptr<Stage> &S = *I;
57  Err = S->cycleStart();
58  }
59 
60  // Now fetch and execute new instructions.
61  InstRef IR;
62  Stage &FirstStage = *Stages[0];
63  while (!Err && FirstStage.isAvailable(IR))
64  Err = FirstStage.execute(IR);
65 
66  // Update stages in preparation for a new cycle.
67  for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) {
68  const std::unique_ptr<Stage> &S = *I;
69  Err = S->cycleEnd();
70  }
71 
72  return Err;
73 }
74 
75 void Pipeline::appendStage(std::unique_ptr<Stage> S) {
76  assert(S && "Invalid null stage in input!");
77  if (!Stages.empty()) {
78  Stage *Last = Stages.back().get();
79  Last->setNextInSequence(S.get());
80  }
81 
82  Stages.push_back(std::move(S));
83 }
84 
85 void Pipeline::notifyCycleBegin() {
86  LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n');
87  for (HWEventListener *Listener : Listeners)
88  Listener->onCycleBegin();
89 }
90 
91 void Pipeline::notifyCycleEnd() {
92  LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n");
93  for (HWEventListener *Listener : Listeners)
94  Listener->onCycleEnd();
95 }
96 } // namespace mca.
97 } // namespace llvm
void addEventListener(HWEventListener *Listener)
Definition: Pipeline.cpp:25
This class represents lattice values for constants.
Definition: AllocatorList.h:24
virtual Error execute(InstRef &IR)=0
The primary action that this stage performs on instruction IR.
Subclass of Error for the sole purpose of identifying the success path in the type system...
Definition: Error.h:325
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:478
Tagged union holding either a T or a Error.
Definition: CachePruning.h:23
This file implements an ordered container of stages that simulate the pipeline of a hardware backend...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual bool isAvailable(const InstRef &IR) const
Returns true if it can execute IR during this cycle.
Definition: Stage.h:43
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1193
This file defines the main interface for hardware event listeners.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Expected< unsigned > run()
Returns the total number of simulated cycles.
Definition: Pipeline.cpp:38
#define I(x, y, z)
Definition: MD5.cpp:58
void appendStage(std::unique_ptr< Stage > S)
Definition: Pipeline.cpp:75
void setNextInSequence(Stage *NextStage)
Definition: Stage.h:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Lightweight error class with error context and mandatory checking.
Definition: Error.h:158
#define LLVM_DEBUG(X)
Definition: Debug.h:123
Statically lint checks LLVM IR
Definition: Lint.cpp:193