AMDGPUAsmParser.cpp File Reference

#include "AMDGPU.h"
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "MCTargetDesc/AMDGPUTargetStreamer.h"
#include "SIDefines.h"
#include "SIInstrInfo.h"
#include "Utils/AMDGPUAsmUtils.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "Utils/AMDKernelCodeTUtils.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/TargetParser.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstring>
#include <iterator>
#include <map>
#include <memory>
#include <string>
#include "AMDGPUGenAsmMatcher.inc"

Go to the source code of this file.

Macros
#define	PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE)
#define	GET_REGISTER_MATCHER
#define	GET_MATCHER_IMPLEMENTATION
#define	GET_MNEMONIC_SPELL_CHECKER
Auto-generated Match Functions
{
#define	GET_ASSEMBLER_HEADER

Enumerations
enum	RegisterKind

Functions
static const fltSemantics *	getFltSemantics (unsigned Size)
static const fltSemantics *	getFltSemantics (MVT VT)
static const fltSemantics *	getOpFltSemantics (uint8_t OperandType)
static bool	canLosslesslyConvertToFPType (APFloat &FPLiteral, MVT VT)
static int	getRegClass (RegisterKind Is, unsigned RegWidth)
static unsigned	getSpecialRegForName (StringRef RegName)
static std::string	AMDGPUMnemonicSpellCheck (StringRef S, uint64_t FBS, unsigned VariantID=0)
static void	addOptionalImmOperand (MCInst &Inst, const OperandVector &Operands, AMDGPUAsmParser::OptionalImmIndexMap &OptionalIdx, AMDGPUOperand::ImmTy ImmT, int64_t Default=0)
static bool	encodeCnt (const AMDGPU::IsaVersion ISA, int64_t &IntVal, int64_t CntVal, bool Saturate, unsigned(*encode)(const IsaVersion &Version, unsigned, unsigned), unsigned(*decode)(const IsaVersion &Version, unsigned))
static LLVM_READNONE unsigned	encodeBitmaskPerm (const unsigned AndMask, const unsigned OrMask, const unsigned XorMask)
static bool	ConvertOmodMul (int64_t &Mul)
static bool	ConvertOmodDiv (int64_t &Div)
static bool	ConvertBoundCtrl (int64_t &BoundCtrl)
static bool	isRegOrImmWithInputMods (const MCInstrDesc &Desc, unsigned OpNum)
void	LLVMInitializeAMDGPUAsmParser ()
	Force static initialization. More...

Variables
static const OptionalOperand	AMDGPUOptionalOperandTable []

Macro Definition Documentation

GET_ASSEMBLER_HEADER

#define GET_ASSEMBLER_HEADER

Definition at line 841 of file AMDGPUAsmParser.cpp.

GET_MATCHER_IMPLEMENTATION

#define GET_MATCHER_IMPLEMENTATION

Definition at line 5505 of file AMDGPUAsmParser.cpp.

GET_MNEMONIC_SPELL_CHECKER

#define GET_MNEMONIC_SPELL_CHECKER

Definition at line 5506 of file AMDGPUAsmParser.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 5504 of file AMDGPUAsmParser.cpp.

PARSE_BITS_ENTRY

#define PARSE_BITS_ENTRY	(		FIELD,
			ENTRY,
			VALUE,
			RANGE
	)

Value:

if (!isUInt<ENTRY##_WIDTH>(VALUE))                                           \
    return OutOfRangeError(RANGE);                                             \
  AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);

Referenced by getSpecialRegForName().

Enumeration Type Documentation

RegisterKind

enum RegisterKind

Definition at line 72 of file AMDGPUAsmParser.cpp.

Function Documentation

addOptionalImmOperand()

static void addOptionalImmOperand ( MCInst &  Inst, const OperandVector &  Operands, AMDGPUAsmParser::OptionalImmIndexMap &  OptionalIdx, AMDGPUOperand::ImmTy  ImmT, int64_t  Default = 0  )

static

Definition at line 3483 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::addOperand(), assert(), llvm::AsmToken::Colon, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::Format, llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::AsmToken::Identifier, llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MCOperand::setReg(), llvm::SmallVectorBase::size(), and llvm::MCInst::size().

Referenced by encodeBitmaskPerm(), and isRegOrImmWithInputMods().

AMDGPUMnemonicSpellCheck()

static std::string AMDGPUMnemonicSpellCheck ( StringRef  S, uint64_t  FBS, unsigned  VariantID = 0  )

static

Referenced by getSpecialRegForName().

canLosslesslyConvertToFPType()

static bool canLosslesslyConvertToFPType ( APFloat &  FPLiteral, MVT  VT  )

static

Definition at line 1228 of file AMDGPUAsmParser.cpp.

References llvm::Literal, and llvm::Warning.

ConvertBoundCtrl()

static bool ConvertBoundCtrl ( int64_t &  BoundCtrl )

static

Definition at line 4779 of file AMDGPUAsmParser.cpp.

ConvertOmodDiv()

static bool ConvertOmodDiv ( int64_t &  Div )

static

Definition at line 4765 of file AMDGPUAsmParser.cpp.

ConvertOmodMul()

static bool ConvertOmodMul ( int64_t &  Mul )

static

Definition at line 4757 of file AMDGPUAsmParser.cpp.

encodeBitmaskPerm()

static LLVM_READNONE unsigned encodeBitmaskPerm ( const unsigned  AndMask, const unsigned  OrMask, const unsigned  XorMask  )

static

Definition at line 4284 of file AMDGPUAsmParser.cpp.

References addOptionalImmOperand(), assert(), llvm::MCInst::begin(), llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT, llvm::AMDGPU::Swizzle::BITMASK_MAX, llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT, llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC, llvm::AMDGPU::Swizzle::BITMASK_WIDTH, llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT, llvm::AsmToken::Colon, llvm::AsmToken::Comma, llvm::MCSymbolRefExpr::create(), E, llvm::AMDGPU::getMUBUFNoLdsInst(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInst::getOpcode(), I, llvm::AMDGPU::Swizzle::ID_BITMASK_PERM, llvm::AMDGPU::Swizzle::ID_BROADCAST, llvm::AMDGPU::Swizzle::ID_QUAD_PERM, llvm::AMDGPU::Swizzle::ID_REVERSE, llvm::AMDGPU::Swizzle::ID_SWAP, llvm::AsmToken::Identifier, llvm::AMDGPU::SendMsg::IdSymbolic, llvm::MCInst::insert(), llvm::AsmToken::Integer, llvm::isPowerOf2_64(), llvm::isUInt< 16 >(), llvm::isUInt< 32 >(), llvm::isUInt< 8 >(), llvm::AMDGPU::Swizzle::LANE_MAX, llvm::AMDGPU::Swizzle::LANE_NUM, llvm::AMDGPU::Swizzle::LANE_SHIFT, llvm_unreachable, llvm::AsmToken::LParen, llvm::BitmaskEnumDetail::Mask(), llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPU::Swizzle::QUAD_PERM_ENC, llvm::AsmToken::RParen, llvm::MCInst::setOpcode(), llvm::SmallVectorBase::size(), and llvm::StringRef::size().

encodeCnt()

static bool encodeCnt ( const AMDGPU::IsaVersion  ISA, int64_t &  IntVal, int64_t  CntVal, bool  Saturate, unsigned(*)(const IsaVersion &Version, unsigned, unsigned)  encode, unsigned(*)(const IsaVersion &Version, unsigned)  decode  )

static

Definition at line 3697 of file AMDGPUAsmParser.cpp.

References llvm::AsmToken::Amp, assert(), llvm::StringSwitch< T, R >::Case(), llvm::AsmToken::Comma, llvm::StringRef::data(), decode(), llvm::AMDGPU::decodeExpcnt(), llvm::AMDGPU::decodeLgkmcnt(), llvm::AMDGPU::decodeVmcnt(), llvm::StringSwitch< T, R >::Default(), llvm::StringRef::drop_back(), llvm::StringRef::drop_front(), llvm::AMDGPU::encodeExpcnt(), llvm::AMDGPU::encodeLgkmcnt(), llvm::AMDGPU::encodeVmcnt(), llvm::AsmToken::EndOfStatement, llvm::StringRef::endswith(), F(), llvm::Failed(), llvm::StringRef::getAsInteger(), llvm::getCPU(), llvm::SMLoc::getFromPointer(), llvm::AMDGPU::getIsaVersion(), llvm::AMDGPU::getWaitcntBitMask(), llvm::AMDGPU::SendMsg::ID_GAPS_FIRST_, llvm::AMDGPU::SendMsg::ID_GAPS_LAST_, llvm::AMDGPU::SendMsg::ID_GS, llvm::AMDGPU::SendMsg::ID_GS_DONE, llvm::AMDGPU::SendMsg::ID_INTERRUPT, llvm::AMDGPU::SendMsg::ID_SHIFT_, llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_, llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX9_, llvm::AMDGPU::Hwreg::ID_SYMBOLIC_LAST_, llvm::AMDGPU::SendMsg::ID_SYSMSG, llvm::AMDGPU::SendMsg::ID_UNKNOWN_, llvm::AsmToken::Identifier, llvm::AMDGPU::SendMsg::IdSymbolic, llvm::AsmToken::Integer, llvm::AsmToken::is(), llvm::AMDGPU::isCI(), llvm::AMDGPU::isSI(), llvm::isUInt< 16 >(), llvm::AMDGPU::isVI(), LLVM_READNONE, llvm::AsmToken::LParen, llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_, llvm::AMDGPU::Hwreg::OFFSET_SHIFT_, llvm::AMDGPU::SendMsg::OP_GS_FIRST_, llvm::AMDGPU::SendMsg::OP_GS_LAST_, llvm::AMDGPU::SendMsg::OP_GS_NOP, llvm::AMDGPU::SendMsg::OP_SHIFT_, llvm::AMDGPU::SendMsg::OP_SYS_FIRST_, llvm::AMDGPU::SendMsg::OP_SYS_LAST_, llvm::AMDGPU::SendMsg::OP_UNKNOWN_, Operation, llvm::AMDGPU::SendMsg::OpGsSymbolic, llvm::AMDGPU::SendMsg::OpSysSymbolic, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AsmToken::RParen, llvm::StringRef::startswith(), llvm::AMDGPU::SendMsg::STREAM_ID_DEFAULT_, llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_, llvm::AMDGPU::SendMsg::STREAM_ID_LAST_, llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_, llvm::AsmToken::String, llvm::StringRef::take_back(), llvm::AMDGPU::Hwreg::WIDTH_M1_DEFAULT_, and llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_.

getFltSemantics() [1/2]

static const fltSemantics* getFltSemantics ( unsigned  Size )

static

Definition at line 1183 of file AMDGPUAsmParser.cpp.

getFltSemantics() [2/2]

static const fltSemantics* getFltSemantics ( MVT  VT )

static

Definition at line 1196 of file AMDGPUAsmParser.cpp.

getOpFltSemantics()

static const fltSemantics* getOpFltSemantics ( uint8_t  OperandType )

static

Definition at line 1200 of file AMDGPUAsmParser.cpp.

getRegClass()

static int getRegClass ( RegisterKind  Is, unsigned  RegWidth  )

static

Definition at line 1559 of file AMDGPUAsmParser.cpp.

Referenced by canTurnIntoCOPY(), countMCSymbolRefExpr(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::getOpSize(), getRegClassFromGRPhysReg(), getSpecialRegForName(), llvm::SIRegisterInfo::isSGPRClassID(), llvm::MipsSEInstrInfo::loadImmediate(), MakeM0Inst(), and llvm::X86InstrInfo::unfoldMemoryOperand().

getSpecialRegForName()

static unsigned getSpecialRegForName ( StringRef  RegName )

static

Definition at line 1592 of file AMDGPUAsmParser.cpp.

References llvm::Triple::amdgcn, AMDGPUMnemonicSpellCheck(), llvm::Triple::AMDHSA, AMDHSA_BITS_SET, assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::APFloat::bitcastToAPInt(), llvm::BitsToDouble(), llvm::StringSwitch< T, R >::Case(), llvm::APFloat::changeSign(), llvm::AsmToken::Colon, llvm::AsmToken::Comma, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2, llvm::countPopulation(), llvm::MCConstantExpr::create(), llvm::AMDGPUAsmVariants::DEFAULT, llvm::StringSwitch< T, R >::Default(), llvm::SIInstrFlags::DPP, llvm::AMDGPUAsmVariants::DPP, llvm::AMDGPU::SDWA::DWORD, llvm::MCOI::EARLY_CLOBBER, llvm::MCStreamer::EmitInstruction(), llvm::StringMap< char, AllocatorTy >::end(), llvm::AsmToken::EndOfStatement, F(), Features, llvm::StringMap< char, AllocatorTy >::find(), llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG, llvm::SIInstrFlags::FLAT, llvm::SIInstrFlags::Gather4, llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::StringRef::getAsInteger(), llvm::getCPU(), llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor(), llvm::MCOperand::getImm(), llvm::AMDGPU::getIsaVersion(), llvm::AsmToken::getLoc(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCRegisterClass::getNumRegs(), llvm::AMDGPU::IsaInfo::getNumSGPRBlocks(), llvm::AMDGPU::IsaInfo::getNumVGPRBlocks(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::AMDGPU::getOperandSize(), llvm::MCOperand::getReg(), llvm::MCRegisterInfo::getRegClass(), getRegClass(), llvm::MCRegisterClass::getRegister(), llvm::AMDGPU::getRegOperandSize(), llvm::AsmToken::getString(), llvm::getToken(), llvm::MCSymbol::getVariableValue(), llvm::APInt::getZExtValue(), llvm::amdhsa::kernel_descriptor_t::group_segment_fixed_size, llvm::AMDGPU::IsaInfo::hasCodeObjectV3(), llvm::AMDGPU::hasPackedD16(), llvm::AMDGPU::hasXNACK(), llvm::AsmToken::Identifier, llvm::MCInstrDesc::ImplicitUses, llvm::StringSet< AllocatorTy >::insert(), llvm::SIInstrFlags::IntClamp, llvm::AsmToken::Integer, llvm::tgtok::IntVal, llvm::AsmToken::is(), llvm::AMDGPU::isCI(), llvm::MCOperand::isImm(), llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralV216(), llvm::MCOperand::isReg(), llvm::AMDGPU::isRegIntersect(), llvm::AMDGPU::isSGPR(), llvm::AMDGPU::isSI(), llvm::AMDGPU::isSISrcOperand(), llvm::isUInt(), llvm::MCSymbol::isVariable(), llvm::amdhsa::kernel_descriptor_t::kernel_code_properties, llvm::AsmToken::LBrac, llvm_unreachable, llvm::AsmToken::LParen, llvm::AMDGPU::IsaVersion::Major, llvm::makeArrayRef(), llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), llvm::AMDGPU::mc2PseudoReg(), llvm::SIInstrFlags::MIMG, llvm::AsmToken::Minus, llvm::None, llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs, llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, PARSE_BITS_ENTRY, llvm::AsmToken::Pipe, llvm::amdhsa::kernel_descriptor_t::private_segment_fixed_size, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AsmToken::RBrac, llvm::AsmToken::Real, Reg, llvm::MipsISD::Ret, llvm::AsmToken::RParen, llvm::SIInstrFlags::SDWA, llvm::AMDGPUAsmVariants::SDWA, llvm::AMDGPUAsmVariants::SDWA9, llvm::MCInst::setLoc(), llvm::MCSymbol::setVariableValue(), Size, llvm::SmallVectorBase::size(), llvm::StringRef::size(), llvm::SMRange::Start, llvm::StringRef::startswith(), llvm::raw_string_ostream::str(), llvm::AMDGPU::IsaInfo::streamIsaVersion(), llvm::AsmToken::String, llvm::StringRef::substr(), llvm::AMDGPU::HSAMD::Kernel::Key::SymbolName, TRI, llvm::MCInstrDesc::TSFlags, llvm::IndexedInstrProf::Version, llvm::SIInstrFlags::VOP1, llvm::SIInstrFlags::VOP2, llvm::SIInstrFlags::VOP3, llvm::AMDGPUAsmVariants::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPAsmPrefer32Bit, and llvm::SIInstrFlags::VOPC.

isRegOrImmWithInputMods()

static bool isRegOrImmWithInputMods ( const MCInstrDesc &  Desc, unsigned  OpNum  )

static

Definition at line 4938 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::addOperand(), addOptionalImmOperand(), assert(), llvm::AMDGPU::DPP::BCAST15, llvm::AMDGPU::DPP::BCAST31, llvm::MCInst::begin(), llvm::AMDGPU::SDWA::BYTE_0, llvm::AMDGPU::SDWA::BYTE_1, llvm::AMDGPU::SDWA::BYTE_2, llvm::AMDGPU::SDWA::BYTE_3, llvm::StringSwitch< T, R >::Case(), llvm::AsmToken::Colon, llvm::AsmToken::Comma, llvm::MCOperand::createImm(), llvm::StringSwitch< T, R >::Default(), llvm::SIInstrFlags::DPP, llvm::AMDGPU::SDWA::DWORD, E, llvm::MCOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), I, llvm::AsmToken::Identifier, llvm::MCInst::insert(), llvm::isInt< 16 >(), llvm::SIInstrFlags::IsPacked, llvm::isUInt< 16 >(), llvm::AMDGPU::isVI(), llvm::AsmToken::LBrac, llvm_unreachable, llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::MCInstrDesc::NumOperands, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::cl::Prefix, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPU::DPP::QUAD_PERM_FIRST, llvm::AMDGPU::DPP::QUAD_PERM_LAST, llvm::AsmToken::RBrac, llvm::MCOperandInfo::RegClass, llvm::AMDGPU::DPP::ROW_HALF_MIRROR, llvm::AMDGPU::DPP::ROW_MIRROR, llvm::AMDGPU::DPP::ROW_ROR0, llvm::AMDGPU::DPP::ROW_ROR_FIRST, llvm::AMDGPU::DPP::ROW_ROR_LAST, llvm::AMDGPU::DPP::ROW_SHL0, llvm::AMDGPU::DPP::ROW_SHL_FIRST, llvm::AMDGPU::DPP::ROW_SHL_LAST, llvm::AMDGPU::DPP::ROW_SHR0, llvm::AMDGPU::DPP::ROW_SHR_FIRST, llvm::AMDGPU::DPP::ROW_SHR_LAST, llvm::MCOperand::setImm(), llvm::SmallVectorBase::size(), llvm::MCOI::TIED_TO, llvm::MCInstrDesc::TSFlags, llvm::AMDGPU::SDWA::UNUSED_PAD, llvm::AMDGPU::SDWA::UNUSED_PRESERVE, llvm::AMDGPU::SDWA::UNUSED_SEXT, llvm::SIInstrFlags::VOP1, llvm::SIInstrFlags::VOP2, llvm::SIInstrFlags::VOPC, llvm::AMDGPU::DPP::WAVE_ROL1, llvm::AMDGPU::DPP::WAVE_ROR1, llvm::AMDGPU::DPP::WAVE_SHL1, llvm::AMDGPU::DPP::WAVE_SHR1, llvm::AMDGPU::SDWA::WORD_0, and llvm::AMDGPU::SDWA::WORD_1.

LLVMInitializeAMDGPUAsmParser()

void LLVMInitializeAMDGPUAsmParser

(

)

Force static initialization.

Definition at line 5499 of file AMDGPUAsmParser.cpp.

References B, llvm::getTheAMDGPUTarget(), and llvm::getTheGCNTarget().

Variable Documentation

AMDGPUOptionalOperandTable

const OptionalOperand AMDGPUOptionalOperandTable[]

static

Definition at line 4794 of file AMDGPUAsmParser.cpp.