LLVM  8.0.1
MipsRegisterBankInfo.h
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1 //===- MipsRegisterBankInfo.h -----------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the targeting of the RegisterBankInfo class for Mips.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSREGISTERBANKINFO_H
16 
18 
19 #define GET_REGBANK_DECLARATIONS
20 #include "MipsGenRegisterBank.inc"
21 
22 namespace llvm {
23 
24 class TargetRegisterInfo;
25 
27 #define GET_TARGET_REGBANK_CLASS
28 #include "MipsGenRegisterBank.inc"
29 };
30 
31 /// This class provides the information for the target register banks.
33 public:
35 
36  const RegisterBank &
37  getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
38 
39  const InstructionMapping &
40  getInstrMapping(const MachineInstr &MI) const override;
41 };
42 } // end namespace llvm
43 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:24
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned const TargetRegisterInfo * TRI
Holds all the information related to register banks.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class provides the information for the target register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:29
Representation of each machine instruction.
Definition: MachineInstr.h:64
IRTranslator LLVM IR MI
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.