AMDGPURegisterBankInfo.cpp File Reference

This file implements the targeting of the RegisterBankInfo class for AMDGPU. More...

#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "AMDGPUGenRegisterBank.inc"
#include "AMDGPUGenRegisterBankInfo.def"

Include dependency graph for AMDGPURegisterBankInfo.cpp:

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Macros
#define	GET_TARGET_REGBANK_IMPL

Functions
static bool	isConstant (const MachineOperand &MO, int64_t &C)
static bool	isInstrUniform (const MachineInstr &MI)

Detailed Description

This file implements the targeting of the RegisterBankInfo class for AMDGPU.

Todo:

This should be generated by TableGen.

Definition in file AMDGPURegisterBankInfo.cpp.

Macro Definition Documentation

GET_TARGET_REGBANK_IMPL

#define GET_TARGET_REGBANK_IMPL

Definition at line 26 of file AMDGPURegisterBankInfo.cpp.

Function Documentation

isConstant()

static bool isConstant ( const MachineOperand &  MO, int64_t &  C  )

static

Definition at line 55 of file AMDGPURegisterBankInfo.cpp.

References C, llvm::tgtok::Def, llvm::MachineOperand::getCImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::ConstantInt::getSExtValue(), llvm::MachineRegisterInfo::getVRegDef(), and MRI.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping().

isInstrUniform()

static bool isInstrUniform ( const MachineInstr &  MI )

static

Definition at line 248 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::Default, E, llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), llvm::getSizeInBits(), getValueMapping(), llvm::MachineInstr::hasOneMemOperand(), I, llvm::MachineOperand::isIntrinsicID(), llvm::MachineOperand::isReg(), llvm::AMDGPUInstrInfo::isUniformMMO(), llvm::MachineInstr::memoperands_begin(), MI, MRI, Reg, and Size.