17 #ifndef LLVM_CODEGEN_RESOURCEPRIORITYQUEUE_H 18 #define LLVM_CODEGEN_RESOURCEPRIORITYQUEUE_H 28 class ResourcePriorityQueue;
40 std::vector<SUnit> *SUnits;
46 std::vector<unsigned> NumNodesSolelyBlocking;
49 std::vector<SUnit*> Queue;
57 std::vector<unsigned> RegLimit;
67 std::unique_ptr<DFAPacketizer> ResourcesModel;
71 std::vector<SUnit*> Packet;
74 unsigned ParallelLiveRanges;
75 int HorizontalVerticalBalance;
82 void initNodes(std::vector<SUnit> &sunits)
override;
85 NumNodesSolelyBlocking.resize(SUnits->size(), 0);
95 assert(NodeNum < (*SUnits).size());
96 return (*SUnits)[NodeNum].getHeight();
100 assert(NodeNum < NumNodesSolelyBlocking.size());
101 return NumNodesSolelyBlocking[NodeNum];
106 int SUSchedulingCost (
SUnit *SU);
110 void initNumRegDefsLeft(
SUnit *SU);
111 void updateNumRegDefsLeft(
SUnit *SU);
112 int regPressureDelta(
SUnit *SU,
bool RawPressure =
false);
113 int rawRegPressureDelta (
SUnit *SU,
unsigned RCId);
115 bool empty()
const override {
return Queue.empty(); }
117 void push(
SUnit *U)
override;
119 SUnit *pop()
override;
121 void remove(
SUnit *SU)
override;
124 void scheduledNode(
SUnit *SU)
override;
125 bool isResourceAvailable(
SUnit *SU);
126 void reserveResources(
SUnit *SU);
129 void adjustPriorityOfUnscheduledPreds(
SUnit *SU);
131 unsigned numberRCValPredInSU (
SUnit *SU,
unsigned RCId);
132 unsigned numberRCValSuccInSU (
SUnit *SU,
unsigned RCId);
This class represents lattice values for constants.
bool empty() const override
unsigned const TargetRegisterInfo * TRI
void addNode(const SUnit *SU) override
This interface is used to plug different priorities computation algorithms into the list scheduler...
const HexagonInstrInfo * TII
bool isBottomUp() const override
void updateNode(const SUnit *SU) override
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sorting functions for the Available queue.
void releaseState() override
Itinerary data supplied by a subtarget to be used by a target.
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getLatency(unsigned NodeNum) const
bool operator()(const SUnit *LHS, const SUnit *RHS) const
This heuristic is used if DFA scheduling is not desired for some VLIW platform.
unsigned getNumSolelyBlockNodes(unsigned NodeNum) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ResourcePriorityQueue * PQ
Scheduling unit. This is a node in the scheduling DAG.
resource_sort(ResourcePriorityQueue *pq)