15 #define DEBUG_TYPE "hexagon-shuffle" 33 cl::desc(
"Disable Hexagon instruction shuffling"));
35 void HexagonMCShuffler::init(
MCInst &MCB) {
37 MCInst const *Extender =
nullptr;
57 void HexagonMCShuffler::init(
MCInst &MCB,
MCInst const &AddMI,
58 bool bInsertAtFront) {
62 MCInst const *Extender =
nullptr;
88 MCInst const &MI =
I->getDesc();
89 MCInst const *Extender =
I->getExtender();
155 bool doneShuffling =
false;
156 while (possibleDuplexes.
size() > 0 && (!doneShuffling)) {
162 if (MCS.
size() == 1) {
174 if (!doneShuffling) {
186 MCInst const &AddMI,
int fixupCount) {
196 if (fixupCount >= 2) {
218 if (bhasDuplex && bundleSize >= maxBundleSize)
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
This class represents lattice values for constants.
void append(MCInst const &ID, MCInst const *Extender, unsigned S)
bool isBundle(MCInst const &MCI)
bool isImmext(MCInst const &MCI)
bool reshuffleTo(MCInst &MCB)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Context object for machine code objects.
HexagonPacket::iterator iterator
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
Instances of this class represent a single low-level machine instruction.
initializer< Ty > init(const Ty &Val)
MCSubtargetInfo const & STI
Interface to description of machine instruction set.
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
const MCOperand & getOperand(unsigned i) const
LLVM_NODISCARD T pop_back_val()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static MCOperand createInst(const MCInst *Val)
Generic base class for all target subtargets.
size_t bundleSize(MCInst const &MCI)
static cl::opt< bool > DisableShuffle("disable-hexagon-shuffle", cl::Hidden, cl::init(false), cl::desc("Disable Hexagon instruction shuffling"))
bool hasImmExt(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define HEXAGON_PACKET_SIZE
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
void addOperand(const MCOperand &Op)
unsigned getOpcode() const
static MCOperand createImm(int64_t Val)