This class represents the scheduled code. More...

#include "llvm/CodeGen/MachinePipeliner.h"

Public Types
using	sched_iterator = DenseMap< int, std::deque< SUnit * > >::iterator
	Iterators for the cycle to instruction map. More...

using	const_sched_iterator = DenseMap< int, std::deque< SUnit * > >::const_iterator

Public Member Functions
	SMSchedule (MachineFunction *mf)

void	reset ()

void	setInitiationInterval (int ii)
	Set the initiation interval for this schedule. More...

int	getFirstCycle () const
	Return the first cycle in the completed schedule. More...

int	getFinalCycle () const
	Return the last cycle in the finalized schedule. More...

int	earliestCycleInChain (const SDep &Dep)
	Return the cycle of the earliest scheduled instruction in the dependence chain. More...

int	latestCycleInChain (const SDep &Dep)
	Return the cycle of the latest scheduled instruction in the dependence chain. More...

void	computeStart (SUnit SU, int MaxEarlyStart, int MinLateStart, int MinEnd, int MaxStart, int II, SwingSchedulerDAG DAG)
	Compute the scheduling start slot for the instruction. More...

bool	insert (SUnit *SU, int StartCycle, int EndCycle, int II)
	Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached. More...

bool	isScheduledAtStage (SUnit *SU, unsigned StageNum)
	Return true if the instruction is scheduled at the specified stage. More...

int	stageScheduled (SUnit *SU) const
	Return the stage for a scheduled instruction. More...

unsigned	cycleScheduled (SUnit *SU) const
	Return the cycle for a scheduled instruction. More...

unsigned	getMaxStageCount ()
	Return the maximum stage count needed for this schedule. More...

unsigned	getStagesForReg (int Reg, unsigned CurStage)
	Return the max. More...

unsigned	getStagesForPhi (int Reg)
	The number of stages for a Phi is a little different than other instructions. More...

std::deque< SUnit * > &	getInstructions (int cycle)
	Return the instructions that are scheduled at the specified cycle. More...

bool	isValidSchedule (SwingSchedulerDAG *SSD)

void	finalizeSchedule (SwingSchedulerDAG *SSD)
	After the schedule has been formed, call this function to combine the instructions from the different stages/cycles. More...

void	orderDependence (SwingSchedulerDAG SSD, SUnit SU, std::deque< SUnit *> &Insts)
	Order the instructions within a cycle so that the definitions occur before the uses. More...

bool	isLoopCarried (SwingSchedulerDAG *SSD, MachineInstr &Phi)
	Return true if the scheduled Phi has a loop carried operand. More...

bool	isLoopCarriedDefOfUse (SwingSchedulerDAG SSD, MachineInstr Def, MachineOperand &MO)
	Return true if the instruction is a definition that is loop carried and defines the use on the next iteration. More...

void	print (raw_ostream &os) const
	Print the schedule information to the given output. More...

void	dump () const
	Utility function used for debugging to print the schedule. More...

Detailed Description

This class represents the scheduled code.

The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finshes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations.

The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.

Definition at line 468 of file MachinePipeliner.h.

Member Typedef Documentation

◆ const_sched_iterator

using llvm::SMSchedule::const_sched_iterator = DenseMap<int, std::deque<SUnit *> >::const_iterator

Definition at line 539 of file MachinePipeliner.h.

◆ sched_iterator

using llvm::SMSchedule::sched_iterator = DenseMap<int, std::deque<SUnit *> >::iterator

Iterators for the cycle to instruction map.

Definition at line 537 of file MachinePipeliner.h.

Constructor & Destructor Documentation

◆ SMSchedule()

llvm::SMSchedule::SMSchedule ( MachineFunction * mf )

inline

Definition at line 501 of file MachinePipeliner.h.

Member Function Documentation

◆ computeStart()

void SMSchedule::computeStart	(	SUnit *	SU,
		int *	MaxEarlyStart,
		int *	MinLateStart,
		int *	MinEnd,
		int *	MaxStart,
		int	II,
		SwingSchedulerDAG *	DAG
	)

Compute the scheduling start slot for the instruction.

The start slot depends on any predecessor or successor nodes scheduled already.

Definition at line 3227 of file MachinePipeliner.cpp.

References llvm::SwingSchedulerDAG::getDistance(), llvm::SDep::getLatency(), llvm::SDep::getSUnit(), I, llvm::SwingSchedulerDAG::isBackedge(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::max(), and llvm::SUnit::Preds.

Referenced by isIntersect().

◆ cycleScheduled()

unsigned llvm::SMSchedule::cycleScheduled ( SUnit * SU ) const

inline

Return the cycle for a scheduled instruction.

This function normalizes the first cycle to be 0.

Definition at line 557 of file MachinePipeliner.h.

References assert().

Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), and removePhis().

◆ dump()

LLVM_DUMP_METHOD void SMSchedule::dump ( ) const

Utility function used for debugging to print the schedule.

Definition at line 3738 of file MachinePipeliner.cpp.

References llvm::dbgs(), and llvm::Pass::print().

◆ earliestCycleInChain()

int SMSchedule::earliestCycleInChain ( const SDep & Dep )

Return the cycle of the earliest scheduled instruction in the dependence chain.

Definition at line 3168 of file MachinePipeliner.cpp.

References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorBase::empty(), llvm::SDep::getKind(), llvm::SDep::getSUnit(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SDep::Order, llvm::SDep::Output, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SUnit::Preds, and llvm::SmallVectorTemplateBase< T >::push_back().

◆ finalizeSchedule()

void SMSchedule::finalizeSchedule ( SwingSchedulerDAG * SSD )

After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.

That is, this function creates a schedule that represents a single iteration.

Definition at line 3628 of file MachinePipeliner.cpp.

References llvm::SwingSchedulerDAG::applyInstrChange(), llvm::Pass::dump(), E, llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::SUnit::getInstr(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::ScheduleDAGInstrs::getSUnit(), I, llvm::MachineOperand::isDef(), llvm::MachineInstr::isPHI(), llvm::MachineOperand::isReg(), LLVM_DEBUG, llvm::max(), MRI, Reg, llvm::ScheduleDAG::SUnits, and UseMI.

Referenced by isIntersect().

◆ getFinalCycle()

int llvm::SMSchedule::getFinalCycle ( ) const

inline

Return the last cycle in the finalized schedule.

Definition at line 522 of file MachinePipeliner.h.

Referenced by isIntersect().

◆ getFirstCycle()

int llvm::SMSchedule::getFirstCycle ( ) const

inline

Return the first cycle in the completed schedule.

This can be a negative value.

Definition at line 519 of file MachinePipeliner.h.

Referenced by isIntersect().

◆ getInstructions()

std::deque<SUnit *>& llvm::SMSchedule::getInstructions ( int cycle )

inline

Return the instructions that are scheduled at the specified cycle.

Definition at line 591 of file MachinePipeliner.h.

References llvm::tgtok::Def, llvm::Pass::dump(), and llvm::Pass::print().

Referenced by isIntersect().

◆ getMaxStageCount()

unsigned llvm::SMSchedule::getMaxStageCount ( )

inline

Return the maximum stage count needed for this schedule.

Definition at line 564 of file MachinePipeliner.h.

Referenced by isIntersect(), removePhis(), and llvm::SwingSchedulerDAG::schedule().

◆ getStagesForPhi()

unsigned llvm::SMSchedule::getStagesForPhi ( int Reg )

inline

The number of stages for a Phi is a little different than other instructions.

The minimum value computed in RegToStageDiff is 1 because we assume the Phi is needed for at least 1 iteration. This is not the case if the loop value is scheduled prior to the Phi in the same stage. This function returns the number of stages or iterations needed between the Phi definition and any uses.

Definition at line 583 of file MachinePipeliner.h.

References Reg.

Referenced by hasUseAfterLoop(), and removePhis().

◆ getStagesForReg()

unsigned llvm::SMSchedule::getStagesForReg	(	int	Reg,
		unsigned	CurStage
	)

inline

Return the max.

number of stages/iterations that can occur between a register definition and its uses.

Definition at line 570 of file MachinePipeliner.h.

References Reg.

Referenced by hasUseAfterLoop().

◆ insert()

bool SMSchedule::insert	(	SUnit *	SU,
		int	StartCycle,
		int	EndCycle,
		int	II
	)

Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.

This function returns true if the node is scheduled. This routine may search either forward or backward for a place to insert the instruction based upon the relative values of StartCycle and EndCycle.

Definition at line 3118 of file MachinePipeliner.cpp.

References assert(), llvm::dbgs(), llvm::MachineInstr::dump(), E, llvm::SUnit::getInstr(), llvm::MachineInstr::getOpcode(), I, LLVM_DEBUG, and llvm::ARM_MB::ST.

Referenced by isIntersect().

◆ isLoopCarried()

bool SMSchedule::isLoopCarried	(	SwingSchedulerDAG *	SSD,
		MachineInstr &	Phi
	)

Return true if the scheduled Phi has a loop carried operand.

Definition at line 3409 of file MachinePipeliner.cpp.

References assert(), llvm::MachineInstr::getParent(), getPhiRegs(), llvm::ScheduleDAGInstrs::getSUnit(), llvm::MachineInstr::isPHI(), and MRI.

Referenced by hasUseAfterLoop(), and removePhis().

◆ isLoopCarriedDefOfUse()

bool SMSchedule::isLoopCarriedDefOfUse	(	SwingSchedulerDAG *	SSD,
		MachineInstr *	Def,
		MachineOperand &	MO
	)

Return true if the instruction is a definition that is loop carried and defines the use on the next iteration.

v1 = phi(v2, v3) (Def) v3 = op v1 (MO) = v1 If MO appears before Def, then then v1 and v3 may get assigned to the same register.

Definition at line 3437 of file MachinePipeliner.cpp.

References getLoopPhiReg(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineInstr::isPHI(), llvm::MachineOperand::isReg(), and MRI.

◆ isScheduledAtStage()

bool llvm::SMSchedule::isScheduledAtStage	(	SUnit *	SU,
		unsigned	StageNum
	)

inline

Return true if the instruction is scheduled at the specified stage.

Definition at line 542 of file MachinePipeliner.h.

Referenced by isIntersect().

◆ isValidSchedule()

bool SMSchedule::isValidSchedule ( SwingSchedulerDAG * SSD )

Definition at line 3463 of file MachinePipeliner.cpp.

References llvm::any_of(), assert(), llvm::dbgs(), llvm::SUnit::getInstr(), llvm::SDep::getSUnit(), llvm::SUnit::hasPhysRegDefs, llvm::MachineInstr::isPHI(), LLVM_DEBUG, llvm::lower_bound(), llvm::SUnit::NodeNum, llvm::NodeOrder, llvm::SUnit::Preds, SI, llvm::sort(), llvm::ARM_MB::ST, llvm::SUnit::Succs, and llvm::ScheduleDAG::SUnits.

Referenced by isIntersect().

◆ latestCycleInChain()

int SMSchedule::latestCycleInChain ( const SDep & Dep )

Return the cycle of the latest scheduled instruction in the dependence chain.

Definition at line 3191 of file MachinePipeliner.cpp.

References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorBase::empty(), llvm::SDep::getKind(), llvm::SDep::getSUnit(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::max(), llvm::SDep::Order, llvm::SDep::Output, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T >::push_back(), SI, and llvm::SUnit::Succs.

◆ orderDependence()

void SMSchedule::orderDependence	(	SwingSchedulerDAG *	SSD,
		SUnit *	SU,
		std::deque< SUnit *> &	Insts
	)

Order the instructions within a cycle so that the definitions occur before the uses.

Returns true if the instruction is added to the start of the list, or false if added to the end.

Definition at line 3288 of file MachinePipeliner.cpp.

References E, llvm::SUnit::getInstr(), llvm::SwingSchedulerDAG::getInstrBaseReg(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::SDep::Order, P, llvm::SUnit::Preds, Reg, llvm::ARM_MB::ST, and llvm::SUnit::Succs.

◆ print()

void SMSchedule::print ( raw_ostream & os ) const

Print the schedule information to the given output.

Definition at line 3723 of file MachinePipeliner.cpp.

References llvm::SUnit::getInstr(), llvm::SUnit::NodeNum, and llvm::MachineInstr::print().

◆ reset()

void llvm::SMSchedule::reset ( )

inline

Definition at line 505 of file MachinePipeliner.h.

References llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::clear().

Referenced by isIntersect().

◆ setInitiationInterval()

void llvm::SMSchedule::setInitiationInterval ( int ii )

inline

Set the initiation interval for this schedule.

Definition at line 515 of file MachinePipeliner.h.

Referenced by isIntersect().

◆ stageScheduled()

int llvm::SMSchedule::stageScheduled ( SUnit * SU ) const

inline

Return the stage for a scheduled instruction.

Return -1 if the instruction has not been scheduled.

Definition at line 548 of file MachinePipeliner.h.

Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), hasUseAfterLoop(), isIntersect(), and removePhis().

The documentation for this class was generated from the following files:

include/llvm/CodeGen/MachinePipeliner.h
lib/CodeGen/MachinePipeliner.cpp

Public Types

Public Member Functions

Detailed Description

Member Typedef Documentation

◆ const_sched_iterator

◆ sched_iterator

Constructor & Destructor Documentation

◆ SMSchedule()

Member Function Documentation

◆ computeStart()

◆ cycleScheduled()

◆ dump()

◆ earliestCycleInChain()

◆ finalizeSchedule()

◆ getFinalCycle()

◆ getFirstCycle()

◆ getInstructions()

◆ getMaxStageCount()

◆ getStagesForPhi()

◆ getStagesForReg()

◆ insert()

◆ isLoopCarried()

◆ isLoopCarriedDefOfUse()

◆ isScheduledAtStage()

◆ isValidSchedule()

◆ latestCycleInChain()

◆ orderDependence()

◆ print()

◆ reset()

◆ setInitiationInterval()

◆ stageScheduled()