22 #define DEBUG_TYPE "machine-scheduler" 29 for (
auto &SU : *
this) {
51 PredMBB = (*
I == MBB ?
nullptr : *
I);
55 &&
"Loop MBB should not consider predecessor outside of loop.");
60 void SystemZPostRASchedStrategy::
64 ((LastEmittedMI !=
nullptr && LastEmittedMI->getParent() == MBB) ?
65 std::next(LastEmittedMI) : MBB->
begin());
67 for (; I != NextBegin; ++
I) {
68 if (I->isPosition() || I->isDebugInstr())
79 assert ((SchedStates.find(NextMBB) == SchedStates.end()) &&
80 "Entering MBB twice?");
96 if (SinglePredMBB ==
nullptr ||
97 SchedStates.find(SinglePredMBB) == SchedStates.end())
103 HazardRec->
copyState(SchedStates[SinglePredMBB]);
109 I != SinglePredMBB->end();
I++) {
111 bool TakenBranch = (
I->isBranch() &&
132 (C->MF->getSubtarget().getInstrInfo())),
133 MBB(nullptr), HazardRec(nullptr) {
140 for (
auto I : SchedStates) {
148 unsigned NumRegionInstrs) {
150 if (Begin->isTerminator())
162 if (Available.empty())
166 if (Available.size() == 1) {
169 return *Available.begin();
173 LLVM_DEBUG(
dbgs() <<
"** Available: "; Available.dump(*HazardRec););
176 for (
auto *SU : Available) {
179 Candidate c(SU, *HazardRec);
182 if (Best.SU ==
nullptr || c < Best) {
188 dbgs() <<
" Height:" << c.SU->getHeight();
dbgs() <<
"\n";);
192 if (!SU->isScheduleHigh && Best.noCost())
196 assert (Best.SU !=
nullptr);
200 SystemZPostRASchedStrategy::Candidate::
217 if (GroupingCost < other.GroupingCost)
219 if (GroupingCost > other.GroupingCost)
223 if (ResourcesCost < other.ResourcesCost)
225 if (ResourcesCost > other.ResourcesCost)
229 if (SU->getHeight() > other.SU->getHeight())
231 if (SU->getHeight() < other.SU->getHeight())
235 if (SU->NodeNum < other.SU->NodeNum)
243 if (Available.size() == 1)
dbgs() <<
"(only one) ";
244 Candidate c(SU, *HazardRec); c.dumpCosts();
dbgs() <<
"\n";);
259 Available.insert(SU);
void releaseTopNode(SUnit *SU) override
SU has had all predecessor dependencies resolved.
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule, or return NULL.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
static void dump(StringRef Title, SpillInfo const &Spills)
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
reverse_iterator rbegin(StringRef path, Style style=Style::native)
Get reverse begin iterator over path.
void initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) override
Called for a region before scheduling.
virtual ~SystemZPostRASchedStrategy()
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
int groupingCost(SUnit *SU) const
Return the cost of decoder grouping for SU.
BlockT * getHeader() const
SystemZHazardRecognizer maintains the state for one MBB during scheduling.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
const MachineOperand * Target
void schedNode(SUnit *SU, bool IsTopNode) override
ScheduleDAGMI has scheduled an instruction - tell HazardRec about it.
void copyState(SystemZHazardRecognizer *Incoming)
Copy counters from end of single predecessor.
bool isUnbuffered
Uses an unbuffered resource.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Summarize the scheduling resources required for an instruction of a particular scheduling class...
int resourcesCost(SUnit *SU)
Return the cost of SU in regards to processor resources usage.
void leaveMBB() override
Tell the strategy that current MBB is done.
void enterMBB(MachineBasicBlock *NextMBB) override
Tell the strategy that MBB is about to be processed.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
void emitInstruction(MachineInstr *MI, bool TakenBranch=false)
Wrap a non-scheduled instruction in an SU and emit it.
pred_iterator pred_begin()
bool isScheduleHigh
True if preferable to schedule high.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
CHAIN = SC CHAIN, Imm128 - System call.
unsigned pred_size() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
TargetSubtargetInfo - Generic base class for all target subtargets.
SystemZPostRASchedStrategy(const MachineSchedContext *C)
Represents a single loop in the control flow graph.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned NodeNum
Entry # of node in the node vector.
MachineBasicBlock::iterator getLastEmittedMI()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool operator<(int64_t V1, const APSInt &V2)
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
static MachineBasicBlock * getSingleSchedPred(MachineBasicBlock *MBB, const MachineLoop *Loop)
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
void dumpSU(SUnit *SU, raw_ostream &OS) const
Scheduling unit. This is a node in the scheduling DAG.