LLVM  8.0.1
Combiner.h
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1 //== ----- llvm/CodeGen/GlobalISel/Combiner.h --------------------- == //
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// This contains common code to drive combines. Combiner Passes will need to
11 /// setup a CombinerInfo and call combineMachineFunction.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINER_H
16 #define LLVM_CODEGEN_GLOBALISEL_COMBINER_H
17 
20 
21 namespace llvm {
22 class MachineRegisterInfo;
23 class CombinerInfo;
24 class GISelCSEInfo;
25 class TargetPassConfig;
26 class MachineFunction;
27 
28 class Combiner {
29 public:
31 
32  /// If CSEInfo is not null, then the Combiner will setup observer for
33  /// CSEInfo and instantiate a CSEMIRBuilder. Pass nullptr if CSE is not
34  /// needed.
36 
37 protected:
38  CombinerInfo &CInfo;
39 
42  std::unique_ptr<MachineIRBuilder> Builder;
43 };
44 
45 } // End namespace llvm.
46 
47 #endif // LLVM_CODEGEN_GLOBALISEL_GICOMBINER_H
The CSE Analysis object.
Definition: CSEInfo.h:69
This class represents lattice values for constants.
Definition: AllocatorList.h:24
Combiner(CombinerInfo &CombinerInfo, const TargetPassConfig *TPC)
Definition: Combiner.cpp:82
Target-Independent Code Generator Pass Configuration Options.
CombinerInfo & CInfo
Definition: Combiner.h:38
bool combineMachineInstrs(MachineFunction &MF, GISelCSEInfo *CSEInfo)
If CSEInfo is not null, then the Combiner will setup observer for CSEInfo and instantiate a CSEMIRBui...
Definition: Combiner.cpp:87
std::unique_ptr< MachineIRBuilder > Builder
Definition: Combiner.h:42
const TargetPassConfig * TPC
Definition: Combiner.h:41
This file declares the MachineIRBuilder class.
MachineRegisterInfo * MRI
Definition: Combiner.h:40
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.