Go to the source code of this file.
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| llvm |
| This class represents lattice values for constants.
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static cl::opt< bool > | PreserveTiedOps ("hexbit-keep-tied", cl::Hidden, cl::init(true), cl::desc("Preserve subregisters in tied operands")) |
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static cl::opt< bool > | GenExtract ("hexbit-extract", cl::Hidden, cl::init(true), cl::desc("Generate extract instructions")) |
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static cl::opt< bool > | GenBitSplit ("hexbit-bitsplit", cl::Hidden, cl::init(true), cl::desc("Generate bitsplit instructions")) |
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static cl::opt< unsigned > | MaxExtract ("hexbit-max-extract", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max())) |
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static unsigned | CountExtract = 0 |
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static cl::opt< unsigned > | MaxBitSplit ("hexbit-max-bitsplit", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max())) |
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static unsigned | CountBitSplit = 0 |
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hexagon bit | simplify |
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hexagon bit Hexagon bit | simplification |
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hexagon bit Hexagon bit | false |
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◆ DEBUG_TYPE
#define DEBUG_TYPE "hexbit" |
◆ INITIALIZE_PASS()
INITIALIZE_PASS |
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HexagonLoopRescheduling |
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"hexagon-loop-resched" |
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"Hexagon Loop Rescheduling" |
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false |
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false |
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Definition at line 2943 of file HexagonBitSimplify.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), B, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), E, F(), llvm::find(), llvm::find_if(), G, llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getVRegDef(), Groups, I, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::BitTracker::BitValue::is(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isPHI(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isTerminator(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), LLVM_DEBUG, llvm::BitTracker::BitValue::One, P, llvm::BitTracker::BitRef::Pos, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::pred_end(), llvm::MachineBasicBlock::pred_size(), llvm::printMBBReference(), llvm::printReg(), llvm::BitTracker::BitValue::Ref, llvm::BitTracker::BitValue::RefI, llvm::BitTracker::BitRef::Reg, llvm::BitTracker::run(), SI, llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::MachineBasicBlock::succ_size(), llvm::BitTracker::trace(), llvm::BitTracker::BitValue::Type, llvm::MachineRegisterInfo::use_begin(), llvm::MachineRegisterInfo::use_end(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::RISCVFenceField::W, and llvm::BitTracker::RegisterCell::width().
◆ INITIALIZE_PASS_BEGIN()
◆ CountBitSplit
◆ CountExtract
◆ false
hexagon bit Hexagon bit false |
◆ GenBitSplit
◆ GenExtract
◆ MaxBitSplit
◆ MaxExtract
◆ PreserveTiedOps
cl::opt<bool> PreserveTiedOps("hexbit-keep-tied", cl::Hidden, cl::init(true), cl::desc("Preserve subregisters in tied operands")) |
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◆ simplification
hexagon bit Hexagon bit simplification |
◆ simplify