35 case TargetOpcode::G_ADD:
36 case TargetOpcode::G_AND:
37 case TargetOpcode::G_ASHR:
38 case TargetOpcode::G_LSHR:
39 case TargetOpcode::G_MUL:
40 case TargetOpcode::G_OR:
41 case TargetOpcode::G_SHL:
42 case TargetOpcode::G_SUB:
43 case TargetOpcode::G_XOR:
44 case TargetOpcode::G_UDIV:
45 case TargetOpcode::G_SDIV:
46 case TargetOpcode::G_UREM:
47 case TargetOpcode::G_SREM: {
48 assert(DstOps.
size() == 1 &&
"Invalid dst ops");
49 assert(SrcOps.
size() == 2 &&
"Invalid src ops");
50 const DstOp &Dst = DstOps[0];
51 const SrcOp &Src0 = SrcOps[0];
52 const SrcOp &Src1 = SrcOps[1];
MachineIRBuilder()=default
Some constructors for easy use.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
This class represents lattice values for constants.
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
An MIRBuilder which does trivial constant folding of binary ops.
size_t size() const
size - Get the array size.
Helper class to build MachineInstr.
virtual ~ConstantFoldingMIRBuilder()=default
This file declares the MachineIRBuilder class.
MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef< DstOp > DstOps, ArrayRef< SrcOp > SrcOps, Optional< unsigned > Flags=None) override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())