|
| void | llvm::AMDGPU::IsaInfo::streamIsaVersion (const MCSubtargetInfo *STI, raw_ostream &Stream) |
| | Streams isa version string for given subtarget STI into Stream. More...
|
| |
| bool | llvm::AMDGPU::IsaInfo::hasCodeObjectV3 (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxWavesPerCU (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxWavesPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxWavesPerEU () |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU) |
| |
| unsigned | llvm::AMDGPU::IsaInfo::getNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs) |
| |
| LLVM_READONLY int16_t | llvm::AMDGPU::getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx) |
| |
| LLVM_READONLY const MIMGBaseOpcodeInfo * | llvm::AMDGPU::getMIMGBaseOpcodeInfo (unsigned BaseOpcode) |
| |
| LLVM_READONLY const MIMGDimInfo * | llvm::AMDGPU::getMIMGDimInfo (unsigned Dim) |
| |
| LLVM_READONLY const MIMGLZMappingInfo * | llvm::AMDGPU::getMIMGLZMappingInfo (unsigned L) |
| |
| int | llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords) |
| |
| int | llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels) |
| |
| int | llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc) |
| |
| int | llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Dwords) |
| |
| int | llvm::AMDGPU::getMUBUFDwords (unsigned Opc) |
| |
| bool | llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc) |
| |
| bool | llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc) |
| |
| bool | llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc) |
| |
| int | llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen) |
| |
| void | llvm::AMDGPU::initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI) |
| |
| amdhsa::kernel_descriptor_t | llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor () |
| |
| bool | llvm::AMDGPU::isGroupSegment (const GlobalValue *GV) |
| |
| bool | llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV) |
| |
| bool | llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV) |
| |
| bool | llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT) |
| |
| int | llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default) |
| |
| std::pair< int, int > | llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired) |
| |
| unsigned | llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version) |
| |
| unsigned | llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version) |
| |
| unsigned | llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version) |
| |
| unsigned | llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version) |
| |
| unsigned | llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt) |
| |
| unsigned | llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt) |
| |
| unsigned | llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt) |
| |
| void | llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) |
| | Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
|
| |
| Waitcnt | llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded) |
| |
| unsigned | llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt) |
| |
| unsigned | llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt) |
| |
| unsigned | llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt) |
| |
| unsigned | llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) |
| | Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
|
| |
| unsigned | llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded) |
| |
| unsigned | llvm::AMDGPU::getInitialPSInputAddr (const Function &F) |
| |
| bool | llvm::AMDGPU::isShader (CallingConv::ID cc) |
| |
| bool | llvm::AMDGPU::isCompute (CallingConv::ID cc) |
| |
| bool | llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC) |
| |
| LLVM_READNONE bool | llvm::AMDGPU::isKernel (CallingConv::ID CC) |
| |
| bool | llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::isSI (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::isCI (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::isVI (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI) |
| |
| bool | llvm::AMDGPU::isSGPR (unsigned Reg, const MCRegisterInfo *TRI) |
| | Is Reg - scalar register. More...
|
| |
| bool | llvm::AMDGPU::isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI) |
| | Is there any intersection between registers. More...
|
| |
| unsigned | llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI) |
| | If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
|
| |
| unsigned | llvm::AMDGPU::mc2PseudoReg (unsigned Reg) |
| | Convert hardware register Reg to a pseudo register. More...
|
| |
| bool | llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo) |
| | Can this operand also contain immediate values? More...
|
| |
| bool | llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo) |
| | Is this floating-point operand? More...
|
| |
| bool | llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo) |
| | Does this opearnd support only inlinable literals? More...
|
| |
| unsigned | llvm::AMDGPU::getRegBitWidth (unsigned RCID) |
| | Get the size in bits of a register from the register class RC. More...
|
| |
| unsigned | llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC) |
| | Get the size in bits of a register from the register class RC. More...
|
| |
| unsigned | llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo) |
| | Get size of register operand. More...
|
| |
| LLVM_READNONE unsigned | llvm::AMDGPU::getOperandSize (const MCOperandInfo &OpInfo) |
| |
| LLVM_READNONE unsigned | llvm::AMDGPU::getOperandSize (const MCInstrDesc &Desc, unsigned OpNo) |
| |
| bool | llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi) |
| | Is this literal inlinable. More...
|
| |
| bool | llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi) |
| |
| bool | llvm::AMDGPU::isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi) |
| |
| bool | llvm::AMDGPU::isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi) |
| |
| bool | llvm::AMDGPU::isArgPassedInSGPR (const Argument *A) |
| |
| int64_t | llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset) |
| |
| bool | llvm::AMDGPU::isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset) |
| |
| bool | llvm::AMDGPU::splitMUBUFOffset (uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, uint32_t Align) |
| |
| bool | llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID) |
| |
