llvm::AArch64ISD Namespace Reference

Enumerations
enum	NodeType : unsigned {   FIRST_NUMBER = ISD::BUILTIN_OP_END, WrapperLarge, CALL, TLSDESC_CALLSEQ,   ADRP, ADR, ADDlow, LOADgot,   RET_FLAG, BRCOND, CSEL, FCSEL,   CSINV, CSNEG, CSINC, THREAD_POINTER,   ADC, SBC, ADDS, SUBS,   ADCS, SBCS, ANDS, CCMP,   CCMN, FCCMP, FCMP, EXTR,   DUP, DUPLANE8, DUPLANE16, DUPLANE32,   DUPLANE64, MOVI, MOVIshift, MOVIedit,   MOVImsl, FMOV, MVNIshift, MVNImsl,   BICi, ORRi, BSL, NEG,   ZIP1, ZIP2, UZP1, UZP2,   TRN1, TRN2, REV16, REV32,   REV64, EXT, VSHL, VLSHR,   VASHR, SQSHL_I, UQSHL_I, SQSHLU_I,   SRSHR_I, URSHR_I, CMEQ, CMGE,   CMGT, CMHI, CMHS, FCMEQ,   FCMGE, FCMGT, CMEQz, CMGEz,   CMGTz, CMLEz, CMLTz, FCMEQz,   FCMGEz, FCMGTz, FCMLEz, FCMLTz,   SADDV, UADDV, SMINV, UMINV,   SMAXV, UMAXV, NOT, BIT,   CBZ, CBNZ, TBZ, TBNZ,   TC_RETURN, PREFETCH, SITOF, UITOF,   NVCAST, SMULL, UMULL, FRECPE,   FRECPS, FRSQRTE, FRSQRTS, LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,   LD3post, LD4post, ST2post, ST3post,   ST4post, LD1x2post, LD1x3post, LD1x4post,   ST1x2post, ST1x3post, ST1x4post, LD1DUPpost,   LD2DUPpost, LD3DUPpost, LD4DUPpost, LD1LANEpost,   LD2LANEpost, LD3LANEpost, LD4LANEpost, ST2LANEpost,   ST3LANEpost, ST4LANEpost }

Enumeration Type Documentation

NodeType

enum llvm::AArch64ISD::NodeType : unsigned

Enumerator
FIRST_NUMBER
WrapperLarge
CALL
TLSDESC_CALLSEQ
ADRP
ADR
ADDlow
LOADgot
RET_FLAG
BRCOND
CSEL
FCSEL
CSINV
CSNEG
CSINC
THREAD_POINTER
ADC
SBC
ADDS
SUBS
ADCS
SBCS
ANDS
CCMP
CCMN
FCCMP
FCMP
EXTR
DUP
DUPLANE8
DUPLANE16
DUPLANE32
DUPLANE64
MOVI
MOVIshift
MOVIedit
MOVImsl
FMOV
MVNIshift
MVNImsl
BICi
ORRi
BSL
NEG
ZIP1
ZIP2
UZP1
UZP2
TRN1
TRN2
REV16
REV32
REV64
EXT
VSHL
VLSHR
VASHR
SQSHL_I
UQSHL_I
SQSHLU_I
SRSHR_I
URSHR_I
CMEQ
CMGE
CMGT
CMHI
CMHS
FCMEQ
FCMGE
FCMGT
CMEQz
CMGEz
CMGTz
CMLEz
CMLTz
FCMEQz
FCMGEz
FCMGTz
FCMLEz
FCMLTz
SADDV
UADDV
SMINV
UMINV
SMAXV
UMAXV
NOT
BIT
CBZ
CBNZ
TBZ
TBNZ
TC_RETURN
PREFETCH
SITOF
UITOF
NVCAST	Natural vector cast. ISD::BITCAST is not natural in the big-endian world w.r.t vectors; which causes additional REV instructions to be generated to compensate for the byte-swapping. But sometimes we do need to re-interpret the data in SIMD vector registers in big-endian mode without emitting such REV instructions.
SMULL
UMULL
FRECPE
FRECPS
FRSQRTE
FRSQRTS
LD2post
LD3post
LD4post
ST2post
ST3post
ST4post
LD1x2post
LD1x3post
LD1x4post
ST1x2post
ST1x3post
ST1x4post
LD1DUPpost
LD2DUPpost
LD3DUPpost
LD4DUPpost
LD1LANEpost
LD2LANEpost
LD3LANEpost
LD4LANEpost
ST2LANEpost
ST3LANEpost
ST4LANEpost

Definition at line 29 of file AArch64ISelLowering.h.