Class Scheduler is responsible for issuing instructions to pipeline resources. More...

#include "llvm/MCA/HardwareUnits/Scheduler.h"

Inheritance diagram for llvm::mca::Scheduler:

Collaboration diagram for llvm::mca::Scheduler:

Public Types
enum	Status { SC_AVAILABLE, SC_LOAD_QUEUE_FULL, SC_STORE_QUEUE_FULL, SC_BUFFERS_FULL, SC_DISPATCH_GROUP_STALL }

Public Member Functions
	Scheduler (const MCSchedModel &Model, LSUnit &Lsu)

	Scheduler (const MCSchedModel &Model, LSUnit &Lsu, std::unique_ptr< SchedulerStrategy > SelectStrategy)

	Scheduler (std::unique_ptr< ResourceManager > RM, LSUnit &Lsu, std::unique_ptr< SchedulerStrategy > SelectStrategy)

Status	isAvailable (const InstRef &IR) const
	Check if the instruction in 'IR' can be dispatched and returns an answer in the form of a Status value. More...

void	dispatch (const InstRef &IR)
	Reserves buffer and LSUnit queue resources that are necessary to issue this instruction. More...

bool	isReady (const InstRef &IR) const
	Returns true if IR is ready to be executed by the underlying pipelines. More...

void	issueInstruction (InstRef &IR, SmallVectorImpl< std::pair< ResourceRef, ResourceCycles >> &Used, SmallVectorImpl< InstRef > &Ready)
	Issue an instruction and populates a vector of used pipeline resources, and a vector of instructions that transitioned to the ready state as a result of this event. More...

bool	mustIssueImmediately (const InstRef &IR) const
	Returns true if IR has to be issued immediately, or if IR is a zero latency instruction. More...

void	cycleEvent (SmallVectorImpl< ResourceRef > &Freed, SmallVectorImpl< InstRef > &Ready, SmallVectorImpl< InstRef > &Executed)
	This routine notifies the Scheduler that a new cycle just started. More...

unsigned	getResourceID (uint64_t Mask) const
	Convert a resource mask into a valid llvm processor resource identifier. More...

InstRef	select ()
	Select the next instruction to issue from the ReadySet. More...

void	dump () const

void	sanityCheck (const InstRef &IR) const

Public Member Functions inherited from llvm::mca::HardwareUnit
	HardwareUnit ()=default

virtual	~HardwareUnit ()

Detailed Description

Class Scheduler is responsible for issuing instructions to pipeline resources.

Internally, it delegates to a ResourceManager the management of processor resources. This class is also responsible for tracking the progress of instructions from the dispatch stage, until the write-back stage.

An instruction dispatched to the Scheduler is initially placed into either the 'WaitSet' or the 'ReadySet' depending on the availability of the input operands.

An instruction is moved from the WaitSet to the ReadySet when register operands become available, and all memory dependencies are met. Instructions that are moved from the WaitSet to the ReadySet transition in state from 'IS_AVAILABLE' to 'IS_READY'.

On every cycle, the Scheduler checks if it can promote instructions from the WaitSet to the ReadySet.

An Instruction is moved from the ReadySet the IssuedSet when it is issued to a (one or more) pipeline(s). This event also causes an instruction state transition (i.e. from state IS_READY, to state IS_EXECUTING). An Instruction leaves the IssuedSet when it reaches the write-back stage.

Definition at line 87 of file Scheduler.h.

Member Enumeration Documentation

◆ Status

enum llvm::mca::Scheduler::Status

Enumerator
SC_AVAILABLE
SC_LOAD_QUEUE_FULL
SC_STORE_QUEUE_FULL
SC_BUFFERS_FULL
SC_DISPATCH_GROUP_STALL

Definition at line 135 of file Scheduler.h.

Constructor & Destructor Documentation

◆ Scheduler() [1/3]

llvm::mca::Scheduler::Scheduler	(	const MCSchedModel &	Model,
		LSUnit &	Lsu
	)

inline

Definition at line 120 of file Scheduler.h.

◆ Scheduler() [2/3]

llvm::mca::Scheduler::Scheduler	(	const MCSchedModel &	Model,
		LSUnit &	Lsu,
		std::unique_ptr< SchedulerStrategy >	SelectStrategy
	)

inline

Definition at line 123 of file Scheduler.h.

◆ Scheduler() [3/3]

llvm::mca::Scheduler::Scheduler	(	std::unique_ptr< ResourceManager >	RM,
		LSUnit &	Lsu,
		std::unique_ptr< SchedulerStrategy >	SelectStrategy
	)

inline

Definition at line 128 of file Scheduler.h.

Member Function Documentation

◆ cycleEvent()

void llvm::mca::Scheduler::cycleEvent	(	SmallVectorImpl< ResourceRef > &	Freed,
		SmallVectorImpl< InstRef > &	Ready,
		SmallVectorImpl< InstRef > &	Executed
	)

This routine notifies the Scheduler that a new cycle just started.

It notifies the underlying ResourceManager that a new cycle just started. Vector Freed is populated with resourceRef related to resources that have changed in state, and that are now available to new instructions. Instructions executed are added to vector Executed, while vector Ready is populated with instructions that have become ready in this new cycle.

Definition at line 183 of file Scheduler.cpp.

References llvm::mca::Instruction::cycleEvent(), and llvm::mca::InstRef::getInstruction().

Referenced by llvm::mca::ExecuteStage::cycleStart().

◆ dispatch()

void llvm::mca::Scheduler::dispatch ( const InstRef & IR )

Reserves buffer and LSUnit queue resources that are necessary to issue this instruction.

Returns true if instruction IR is ready to be issued to the underlying pipelines. Note that this operation cannot fail; it assumes that a previous call to method isAvailable(IR) returned SC_AVAILABLE.

Definition at line 211 of file Scheduler.cpp.

References llvm::mca::InstrDesc::Buffers, llvm::dbgs(), llvm::mca::LSUnit::dispatch(), llvm::mca::InstructionBase::getDesc(), llvm::mca::InstRef::getInstruction(), isReady(), LLVM_DEBUG, llvm::mca::InstrDesc::MayLoad, llvm::mca::InstrDesc::MayStore, and mustIssueImmediately().

Referenced by llvm::mca::ExecuteStage::execute().

◆ dump()

void llvm::mca::Scheduler::dump ( ) const

Definition at line 33 of file Scheduler.cpp.

References llvm::dbgs().

◆ getResourceID()

unsigned llvm::mca::Scheduler::getResourceID ( uint64_t Mask ) const

inline

Convert a resource mask into a valid llvm processor resource identifier.

Definition at line 189 of file Scheduler.h.

References llvm::dump().

Referenced by llvm::mca::ExecuteStage::notifyInstructionIssued(), and llvm::mca::ExecuteStage::notifyReservedOrReleasedBuffers().

◆ isAvailable()

Scheduler::Status llvm::mca::Scheduler::isAvailable ( const InstRef & IR ) const

Check if the instruction in 'IR' can be dispatched and returns an answer in the form of a Status value.

The DispatchStage is responsible for querying the Scheduler before dispatching new instructions. This routine is used for performing such a query. If the instruction 'IR' can be dispatched, then true is returned, otherwise false is returned with Event set to the stall type. Internally, it also checks if the load/store unit is available.

Definition at line 41 of file Scheduler.cpp.

References llvm::mca::InstrDesc::Buffers, D, llvm::mca::Instruction::execute(), llvm::mca::InstructionBase::getDesc(), llvm::mca::InstRef::getInstruction(), IR, llvm::mca::LSUnit::isAvailable(), llvm::mca::Instruction::isExecuted(), llvm::mca::Instruction::isExecuting(), llvm_unreachable, llvm::mca::LSUnit::LSU_AVAILABLE, llvm::mca::LSUnit::LSU_LQUEUE_FULL, llvm::mca::LSUnit::LSU_SQUEUE_FULL, llvm::mca::LSUnit::onInstructionExecuted(), llvm::mca::RS_BUFFER_AVAILABLE, llvm::mca::RS_BUFFER_UNAVAILABLE, llvm::mca::RS_RESERVED, SC_AVAILABLE, SC_BUFFERS_FULL, SC_DISPATCH_GROUP_STALL, SC_LOAD_QUEUE_FULL, and SC_STORE_QUEUE_FULL.

Referenced by llvm::mca::ExecuteStage::isAvailable().

◆ isReady()

bool llvm::mca::Scheduler::isReady ( const InstRef & IR ) const

Returns true if IR is ready to be executed by the underlying pipelines.

This method assumes that IR has been previously dispatched.

Definition at line 240 of file Scheduler.cpp.

References llvm::mca::InstructionBase::getDesc(), llvm::mca::InstRef::getInstruction(), llvm::mca::LSUnit::isReady(), llvm::mca::Instruction::isReady(), llvm::mca::InstrDesc::MayLoad, and llvm::mca::InstrDesc::MayStore.

Referenced by dispatch(), llvm::mca::ExecuteStage::execute(), and issueInstruction().

◆ issueInstruction()

void llvm::mca::Scheduler::issueInstruction	(	InstRef &	IR,
		SmallVectorImpl< std::pair< ResourceRef, ResourceCycles >> &	Used,
		SmallVectorImpl< InstRef > &	Ready
	)

Issue an instruction and populates a vector of used pipeline resources, and a vector of instructions that transitioned to the ready state as a result of this event.

Definition at line 87 of file Scheduler.cpp.

References llvm::mca::InstrDesc::Buffers, E, llvm::SmallVectorImpl< T >::emplace_back(), llvm::mca::InstructionBase::getDesc(), llvm::mca::InstRef::getInstruction(), llvm::mca::InstructionBase::hasDependentUsers(), I, llvm::mca::InstRef::invalidate(), isReady(), llvm::mca::Instruction::isReady(), and llvm::mca::Instruction::update().