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LLVM
8.0.1
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This is the complete list of members for llvm::ARMInstrInfo, including all inherited members.
| AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const | llvm::ARMBaseInstrInfo | |
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override | llvm::ARMBaseInstrInfo | |
| analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override | llvm::ARMBaseInstrInfo | |
| analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override | llvm::ARMBaseInstrInfo | |
| areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override | llvm::ARMBaseInstrInfo | |
| ARMBaseInstrInfo(const ARMSubtarget &STI) | llvm::ARMBaseInstrInfo | explicitprotected |
| ARMInstrInfo(const ARMSubtarget &STI) | llvm::ARMInstrInfo | explicit |
| breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override | llvm::ARMBaseInstrInfo | |
| canCauseFpMLxStall(unsigned Opcode) const | llvm::ARMBaseInstrInfo | inline |
| commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override | llvm::ARMBaseInstrInfo | protected |
| convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override | llvm::ARMBaseInstrInfo | |
| copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const | llvm::ARMBaseInstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override | llvm::ARMBaseInstrInfo | |
| copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const | llvm::ARMBaseInstrInfo | |
| CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override | llvm::ARMBaseInstrInfo | |
| CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override | llvm::ARMBaseInstrInfo | |
| decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::ARMBaseInstrInfo | |
| DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override | llvm::ARMBaseInstrInfo | |
| duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override | llvm::ARMBaseInstrInfo | |
| expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const | llvm::ARMBaseInstrInfo | protected |
| expandPostRAPseudo(MachineInstr &MI) const override | llvm::ARMBaseInstrInfo | |
| FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override | llvm::ARMBaseInstrInfo | |
| getExecutionDomain(const MachineInstr &MI) const override | llvm::ARMBaseInstrInfo | |
| getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override | llvm::ARMBaseInstrInfo | protected |
| getFramePred(const MachineInstr &MI) const | llvm::ARMBaseInstrInfo | inline |
| getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override | llvm::ARMBaseInstrInfo | protected |
| getInstSizeInBytes(const MachineInstr &MI) const override | llvm::ARMBaseInstrInfo | |
| getLDMVariableDefsSize(const MachineInstr &MI) const | llvm::ARMBaseInstrInfo | |
| getNoop(MCInst &NopInst) const override | llvm::ARMInstrInfo | |
| getNumLDMAddresses(const MachineInstr &MI) const | llvm::ARMBaseInstrInfo | |
| getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override | llvm::ARMBaseInstrInfo | |
| getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override | llvm::ARMBaseInstrInfo | |
| getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override | llvm::ARMBaseInstrInfo | |
| getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override | llvm::ARMBaseInstrInfo | |
| getPredicate(const MachineInstr &MI) const | llvm::ARMBaseInstrInfo | inline |
| getRegisterInfo() const override | llvm::ARMInstrInfo | inlinevirtual |
| getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override | llvm::ARMBaseInstrInfo | protected |
| getSerializableBitmaskMachineOperandTargetFlags() const override | llvm::ARMBaseInstrInfo | |
| getSerializableDirectMachineOperandTargetFlags() const override | llvm::ARMBaseInstrInfo | |
| getSubtarget() const | llvm::ARMBaseInstrInfo | inline |
| getUnindexedOpcode(unsigned Opc) const override | llvm::ARMInstrInfo | virtual |
| hasNOP() const | llvm::ARMBaseInstrInfo | |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::ARMBaseInstrInfo | |
| isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const | llvm::ARMBaseInstrInfo | |
| isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const | llvm::ARMBaseInstrInfo | |
| isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const | llvm::ARMBaseInstrInfo | |
| isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const override | llvm::ARMBaseInstrInfo | protected |
| isCPSRDefined(const MachineInstr &MI) | llvm::ARMBaseInstrInfo | static |
| isFpMLxInstruction(unsigned Opcode) const | llvm::ARMBaseInstrInfo | inline |
| isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const | llvm::ARMBaseInstrInfo | |
| isLDMBaseRegInList(const MachineInstr &MI) const | llvm::ARMBaseInstrInfo | |
| isLdstScaledReg(const MachineInstr &MI, unsigned Op) const | llvm::ARMBaseInstrInfo | |
| isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const | llvm::ARMBaseInstrInfo | |
| isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const | llvm::ARMBaseInstrInfo | |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::ARMBaseInstrInfo | |
| isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override | llvm::ARMBaseInstrInfo | |
| isPredicable(const MachineInstr &MI) const override | llvm::ARMBaseInstrInfo | |
| isPredicated(const MachineInstr &MI) const override | llvm::ARMBaseInstrInfo | |
| isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override | llvm::ARMBaseInstrInfo | inline |
| isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override | llvm::ARMBaseInstrInfo | |
| isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override | llvm::ARMBaseInstrInfo | |
| isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override | llvm::ARMBaseInstrInfo | |
| isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override | llvm::ARMBaseInstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::ARMBaseInstrInfo | |
| isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override | llvm::ARMBaseInstrInfo | |
| isSwiftFastImmShift(const MachineInstr *MI) const | llvm::ARMBaseInstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::ARMBaseInstrInfo | |
| optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override | llvm::ARMBaseInstrInfo | |
| optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &SeenMIs, bool) const override | llvm::ARMBaseInstrInfo | |
| PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override | llvm::ARMBaseInstrInfo | |
| produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override | llvm::ARMBaseInstrInfo | |
| reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override | llvm::ARMBaseInstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::ARMBaseInstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::ARMBaseInstrInfo | |
| setExecutionDomain(MachineInstr &MI, unsigned Domain) const override | llvm::ARMBaseInstrInfo | |
| shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override | llvm::ARMBaseInstrInfo | |
| shouldSink(const MachineInstr &MI) const override | llvm::ARMBaseInstrInfo | |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::ARMBaseInstrInfo | |
| SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override | llvm::ARMBaseInstrInfo |
1.8.13