LLVM
8.0.1
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This is the complete list of members for llvm::AMDGPURegisterBankInfo, including all inherited members.
AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI) | llvm::AMDGPURegisterBankInfo | |
applyDefaultMapping(const OperandsMapper &OpdMapper) | llvm::RegisterBankInfo | static |
constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) | llvm::RegisterBankInfo | static |
copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override | llvm::AMDGPURegisterBankInfo | virtual |
DefaultMappingID | llvm::RegisterBankInfo | static |
getInstrAlternativeMappings(const MachineInstr &MI) const override | llvm::AMDGPURegisterBankInfo | virtual |
getInstrMapping(const MachineInstr &MI) const override | llvm::AMDGPURegisterBankInfo | virtual |
getInstrMappingImpl(const MachineInstr &MI) const | llvm::RegisterBankInfo | protected |
getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const | llvm::RegisterBankInfo | inline |
getInvalidInstructionMapping() const | llvm::RegisterBankInfo | inline |
getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | protected |
getNumRegBanks() const | llvm::RegisterBankInfo | inline |
getOperandsMapping(Iterator Begin, Iterator End) const | llvm::RegisterBankInfo | protected |
getOperandsMapping(const SmallVectorImpl< const ValueMapping *> &OpdsMapping) const | llvm::RegisterBankInfo | protected |
getOperandsMapping(std::initializer_list< const ValueMapping *> OpdsMapping) const | llvm::RegisterBankInfo | protected |
getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
getRegBank(unsigned ID) | llvm::RegisterBankInfo | inlineprotected |
getRegBank(unsigned ID) const | llvm::RegisterBankInfo | inline |
getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
getRegBankFromRegClass(const TargetRegisterClass &RC) const override | llvm::AMDGPURegisterBankInfo | virtual |
getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
getValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) const | llvm::RegisterBankInfo | protected |
InstructionMappings typedef | llvm::RegisterBankInfo | |
InvalidMappingID | llvm::RegisterBankInfo | static |
MapOfInstructionMappings | llvm::RegisterBankInfo | mutableprotected |
MapOfOperandsMappings | llvm::RegisterBankInfo | mutableprotected |
MapOfPartialMappings | llvm::RegisterBankInfo | mutableprotected |
MapOfValueMappings | llvm::RegisterBankInfo | mutableprotected |
NumRegBanks | llvm::RegisterBankInfo | protected |
PhysRegMinimalRCs | llvm::RegisterBankInfo | mutableprotected |
RegBanks | llvm::RegisterBankInfo | protected |
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks) | llvm::RegisterBankInfo | protected |
RegisterBankInfo() | llvm::RegisterBankInfo | inlineprotected |
ScalarAddx2 | llvm::RegisterBankInfo | |
VectorAdd | llvm::RegisterBankInfo | |
~RegisterBankInfo()=default | llvm::RegisterBankInfo | virtual |