| AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII) | llvm::AMDGPUDisassembler | inline |
| CommentStream | llvm::MCDisassembler | mutable |
| convertMIMGInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| convertSDWAInst(MCInst &MI) const | llvm::AMDGPUDisassembler | |
| createRegOperand(unsigned int RegId) const | llvm::AMDGPUDisassembler | inline |
| createRegOperand(unsigned RegClassID, unsigned Val) const | llvm::AMDGPUDisassembler | inline |
| createSRegOperand(unsigned SRegClassID, unsigned Val) const | llvm::AMDGPUDisassembler | inline |
| decodeDstOp(const OpWidthTy Width, unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeFPImmed(OpWidthTy Width, unsigned Imm) | llvm::AMDGPUDisassembler | static |
| decodeIntImmed(unsigned Imm) | llvm::AMDGPUDisassembler | static |
| decodeLiteralConstant() const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_128(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_256(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_32(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_512(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_64(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_SReg_64_XEXEC(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VGPR_32(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VReg_128(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VReg_64(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VReg_96(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VS_128(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VS_32(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VS_64(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VSrc16(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeOperand_VSrcV216(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSDWASrc(const OpWidthTy Width, unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSDWASrc16(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSDWASrc32(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSDWAVopcDst(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSpecialReg32(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSpecialReg64(unsigned Val) const | llvm::AMDGPUDisassembler | |
| decodeSrcOp(const OpWidthTy Width, unsigned Val) const | llvm::AMDGPUDisassembler | |
| DecodeStatus enum name | llvm::MCDisassembler | |
| errOperand(unsigned V, const Twine &ErrMsg) const | llvm::AMDGPUDisassembler | inline |
| Fail enum value | llvm::MCDisassembler | |
| getContext() const | llvm::MCDisassembler | inline |
| getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override | llvm::AMDGPUDisassembler | virtual |
| getRegClassName(unsigned RegClassID) const | llvm::AMDGPUDisassembler | |
| getSgprClassId(const OpWidthTy Width) const | llvm::AMDGPUDisassembler | |
| getSubtargetInfo() const | llvm::MCDisassembler | inline |
| getTtmpClassId(const OpWidthTy Width) const | llvm::AMDGPUDisassembler | |
| getTTmpIdx(unsigned Val) const | llvm::AMDGPUDisassembler | |
| getVgprClassId(const OpWidthTy Width) const | llvm::AMDGPUDisassembler | |
| isGFX9() const | llvm::AMDGPUDisassembler | |
| isVI() const | llvm::AMDGPUDisassembler | |
| MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) | llvm::MCDisassembler | inline |
| OPW128 enum value | llvm::AMDGPUDisassembler | |
| OPW16 enum value | llvm::AMDGPUDisassembler | |
| OPW256 enum value | llvm::AMDGPUDisassembler | |
| OPW32 enum value | llvm::AMDGPUDisassembler | |
| OPW512 enum value | llvm::AMDGPUDisassembler | |
| OPW64 enum value | llvm::AMDGPUDisassembler | |
| OPW_FIRST_ enum value | llvm::AMDGPUDisassembler | |
| OPW_LAST_ enum value | llvm::AMDGPUDisassembler | |
| OpWidthTy enum name | llvm::AMDGPUDisassembler | |
| OPWV216 enum value | llvm::AMDGPUDisassembler | |
| setSymbolizer(std::unique_ptr< MCSymbolizer > Symzer) | llvm::MCDisassembler | |
| SoftFail enum value | llvm::MCDisassembler | |
| STI | llvm::MCDisassembler | protected |
| Success enum value | llvm::MCDisassembler | |
| Symbolizer | llvm::MCDisassembler | protected |
| tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const | llvm::MCDisassembler | |
| tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const | llvm::MCDisassembler | |
| tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const | llvm::AMDGPUDisassembler | |
| ~AMDGPUDisassembler() override=default | llvm::AMDGPUDisassembler | |
| ~MCDisassembler() | llvm::MCDisassembler | virtual |
