LLVM  8.0.1
Namespaces | Macros | Enumerations
SIDefines.h File Reference
#include "llvm/MC/MCInstrDesc.h"
Include dependency graph for SIDefines.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Namespaces

 llvm
 This class represents lattice values for constants.
 
 llvm::SIInstrFlags
 
 llvm::AMDGPU
 
 llvm::SIStackID
 
 llvm::SISrcMods
 
 llvm::SIOutMods
 
 llvm::VGPRIndexMode
 
 llvm::AMDGPUAsmVariants
 
 llvm::AMDGPU::EncValues
 
 llvm::AMDGPU::SendMsg
 
 llvm::AMDGPU::Hwreg
 
 llvm::AMDGPU::Swizzle
 
 llvm::AMDGPU::SDWA
 
 llvm::AMDGPU::DPP
 

Macros

#define R_00B028_SPI_SHADER_PGM_RSRC1_PS   0x00B028
 
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS   0x00B02C
 
#define S_00B02C_EXTRA_LDS_SIZE(x)   (((x) & 0xFF) << 8)
 
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS   0x00B128
 
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS   0x00B228
 
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES   0x00B328
 
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS   0x00B428
 
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS   0x00B528
 
#define R_00B848_COMPUTE_PGM_RSRC1   0x00B848
 
#define S_00B028_VGPRS(x)   (((x) & 0x3F) << 0)
 
#define S_00B028_SGPRS(x)   (((x) & 0x0F) << 6)
 
#define R_00B84C_COMPUTE_PGM_RSRC2   0x00B84C
 
#define S_00B84C_SCRATCH_EN(x)   (((x) & 0x1) << 0)
 
#define G_00B84C_SCRATCH_EN(x)   (((x) >> 0) & 0x1)
 
#define C_00B84C_SCRATCH_EN   0xFFFFFFFE
 
#define S_00B84C_USER_SGPR(x)   (((x) & 0x1F) << 1)
 
#define G_00B84C_USER_SGPR(x)   (((x) >> 1) & 0x1F)
 
#define C_00B84C_USER_SGPR   0xFFFFFFC1
 
#define S_00B84C_TRAP_HANDLER(x)   (((x) & 0x1) << 6)
 
#define G_00B84C_TRAP_HANDLER(x)   (((x) >> 6) & 0x1)
 
#define C_00B84C_TRAP_HANDLER   0xFFFFFFBF
 
#define S_00B84C_TGID_X_EN(x)   (((x) & 0x1) << 7)
 
#define G_00B84C_TGID_X_EN(x)   (((x) >> 7) & 0x1)
 
#define C_00B84C_TGID_X_EN   0xFFFFFF7F
 
#define S_00B84C_TGID_Y_EN(x)   (((x) & 0x1) << 8)
 
#define G_00B84C_TGID_Y_EN(x)   (((x) >> 8) & 0x1)
 
#define C_00B84C_TGID_Y_EN   0xFFFFFEFF
 
#define S_00B84C_TGID_Z_EN(x)   (((x) & 0x1) << 9)
 
#define G_00B84C_TGID_Z_EN(x)   (((x) >> 9) & 0x1)
 
#define C_00B84C_TGID_Z_EN   0xFFFFFDFF
 
#define S_00B84C_TG_SIZE_EN(x)   (((x) & 0x1) << 10)
 
#define G_00B84C_TG_SIZE_EN(x)   (((x) >> 10) & 0x1)
 
#define C_00B84C_TG_SIZE_EN   0xFFFFFBFF
 
#define S_00B84C_TIDIG_COMP_CNT(x)   (((x) & 0x03) << 11)
 
#define G_00B84C_TIDIG_COMP_CNT(x)   (((x) >> 11) & 0x03)
 
#define C_00B84C_TIDIG_COMP_CNT   0xFFFFE7FF
 
#define S_00B84C_EXCP_EN_MSB(x)   (((x) & 0x03) << 13)
 
#define G_00B84C_EXCP_EN_MSB(x)   (((x) >> 13) & 0x03)
 
#define C_00B84C_EXCP_EN_MSB   0xFFFF9FFF
 
#define S_00B84C_LDS_SIZE(x)   (((x) & 0x1FF) << 15)
 
#define G_00B84C_LDS_SIZE(x)   (((x) >> 15) & 0x1FF)
 
#define C_00B84C_LDS_SIZE   0xFF007FFF
 
#define S_00B84C_EXCP_EN(x)   (((x) & 0x7F) << 24)
 
#define G_00B84C_EXCP_EN(x)   (((x) >> 24) & 0x7F)
 
#define C_00B84C_EXCP_EN
 
#define R_0286CC_SPI_PS_INPUT_ENA   0x0286CC
 
#define R_0286D0_SPI_PS_INPUT_ADDR   0x0286D0
 
#define R_00B848_COMPUTE_PGM_RSRC1   0x00B848
 
#define S_00B848_VGPRS(x)   (((x) & 0x3F) << 0)
 
#define G_00B848_VGPRS(x)   (((x) >> 0) & 0x3F)
 
#define C_00B848_VGPRS   0xFFFFFFC0
 
#define S_00B848_SGPRS(x)   (((x) & 0x0F) << 6)
 
#define G_00B848_SGPRS(x)   (((x) >> 6) & 0x0F)
 
#define C_00B848_SGPRS   0xFFFFFC3F
 
#define S_00B848_PRIORITY(x)   (((x) & 0x03) << 10)
 
#define G_00B848_PRIORITY(x)   (((x) >> 10) & 0x03)
 
#define C_00B848_PRIORITY   0xFFFFF3FF
 
#define S_00B848_FLOAT_MODE(x)   (((x) & 0xFF) << 12)
 
#define G_00B848_FLOAT_MODE(x)   (((x) >> 12) & 0xFF)
 
#define C_00B848_FLOAT_MODE   0xFFF00FFF
 
#define S_00B848_PRIV(x)   (((x) & 0x1) << 20)
 
#define G_00B848_PRIV(x)   (((x) >> 20) & 0x1)
 
#define C_00B848_PRIV   0xFFEFFFFF
 
#define S_00B848_DX10_CLAMP(x)   (((x) & 0x1) << 21)
 
#define G_00B848_DX10_CLAMP(x)   (((x) >> 21) & 0x1)
 
#define C_00B848_DX10_CLAMP   0xFFDFFFFF
 
#define S_00B848_DEBUG_MODE(x)   (((x) & 0x1) << 22)
 
#define G_00B848_DEBUG_MODE(x)   (((x) >> 22) & 0x1)
 
#define C_00B848_DEBUG_MODE   0xFFBFFFFF
 
#define S_00B848_IEEE_MODE(x)   (((x) & 0x1) << 23)
 
#define G_00B848_IEEE_MODE(x)   (((x) >> 23) & 0x1)
 
#define C_00B848_IEEE_MODE   0xFF7FFFFF
 
#define FP_ROUND_ROUND_TO_NEAREST   0
 
#define FP_ROUND_ROUND_TO_INF   1
 
#define FP_ROUND_ROUND_TO_NEGINF   2
 
#define FP_ROUND_ROUND_TO_ZERO   3
 
#define FP_ROUND_MODE_SP(x)   ((x) & 0x3)
 
#define FP_ROUND_MODE_DP(x)   (((x) & 0x3) << 2)
 
#define FP_DENORM_FLUSH_IN_FLUSH_OUT   0
 
#define FP_DENORM_FLUSH_OUT   1
 
#define FP_DENORM_FLUSH_IN   2
 
#define FP_DENORM_FLUSH_NONE   3
 
#define FP_DENORM_MODE_SP(x)   (((x) & 0x3) << 4)
 
#define FP_DENORM_MODE_DP(x)   (((x) & 0x3) << 6)
 
#define R_00B860_COMPUTE_TMPRING_SIZE   0x00B860
 
#define S_00B860_WAVESIZE(x)   (((x) & 0x1FFF) << 12)
 
#define R_0286E8_SPI_TMPRING_SIZE   0x0286E8
 
#define S_0286E8_WAVESIZE(x)   (((x) & 0x1FFF) << 12)
 
#define R_SPILLED_SGPRS   0x4
 
#define R_SPILLED_VGPRS   0x8
 

Enumerations

enum  : uint64_t {
  llvm::SIInstrFlags::SALU = 1 << 0, llvm::SIInstrFlags::VALU = 1 << 1, llvm::SIInstrFlags::SOP1 = 1 << 2, llvm::SIInstrFlags::SOP2 = 1 << 3,
  llvm::SIInstrFlags::SOPC = 1 << 4, llvm::SIInstrFlags::SOPK = 1 << 5, llvm::SIInstrFlags::SOPP = 1 << 6, llvm::SIInstrFlags::VOP1 = 1 << 7,
  llvm::SIInstrFlags::VOP2 = 1 << 8, llvm::SIInstrFlags::VOPC = 1 << 9, llvm::SIInstrFlags::VOP3 = 1 << 10, llvm::SIInstrFlags::VOP3P = 1 << 12,
  llvm::SIInstrFlags::VINTRP = 1 << 13, llvm::SIInstrFlags::SDWA = 1 << 14, llvm::SIInstrFlags::DPP = 1 << 15, llvm::SIInstrFlags::MUBUF = 1 << 16,
  llvm::SIInstrFlags::MTBUF = 1 << 17, llvm::SIInstrFlags::SMRD = 1 << 18, llvm::SIInstrFlags::MIMG = 1 << 19, llvm::SIInstrFlags::EXP = 1 << 20,
  llvm::SIInstrFlags::FLAT = 1 << 21, llvm::SIInstrFlags::DS = 1 << 22, llvm::SIInstrFlags::VGPRSpill = 1 << 23, llvm::SIInstrFlags::SGPRSpill = 1 << 24,
  llvm::SIInstrFlags::VM_CNT = UINT64_C(1) << 32, llvm::SIInstrFlags::EXP_CNT = UINT64_C(1) << 33, llvm::SIInstrFlags::LGKM_CNT = UINT64_C(1) << 34, llvm::SIInstrFlags::WQM = UINT64_C(1) << 35,
  llvm::SIInstrFlags::DisableWQM = UINT64_C(1) << 36, llvm::SIInstrFlags::Gather4 = UINT64_C(1) << 37, llvm::SIInstrFlags::SOPK_ZEXT = UINT64_C(1) << 38, llvm::SIInstrFlags::SCALAR_STORE = UINT64_C(1) << 39,
  llvm::SIInstrFlags::FIXED_SIZE = UINT64_C(1) << 40, llvm::SIInstrFlags::VOPAsmPrefer32Bit = UINT64_C(1) << 41, llvm::SIInstrFlags::VOP3_OPSEL = UINT64_C(1) << 42, llvm::SIInstrFlags::maybeAtomic = UINT64_C(1) << 43,
  llvm::SIInstrFlags::renamedInGFX9 = UINT64_C(1) << 44, llvm::SIInstrFlags::FPClamp = UINT64_C(1) << 45, llvm::SIInstrFlags::IntClamp = UINT64_C(1) << 46, llvm::SIInstrFlags::ClampLo = UINT64_C(1) << 47,
  llvm::SIInstrFlags::ClampHi = UINT64_C(1) << 48, llvm::SIInstrFlags::IsPacked = UINT64_C(1) << 49, llvm::SIInstrFlags::D16Buf = UINT64_C(1) << 50, llvm::SIInstrFlags::FPDPRounding = UINT64_C(1) << 51
}
 
enum  llvm::SIInstrFlags::ClassFlags {
  llvm::SIInstrFlags::S_NAN = 1 << 0, llvm::SIInstrFlags::Q_NAN = 1 << 1, llvm::SIInstrFlags::N_INFINITY = 1 << 2, llvm::SIInstrFlags::N_NORMAL = 1 << 3,
  llvm::SIInstrFlags::N_SUBNORMAL = 1 << 4, llvm::SIInstrFlags::N_ZERO = 1 << 5, llvm::SIInstrFlags::P_ZERO = 1 << 6, llvm::SIInstrFlags::P_SUBNORMAL = 1 << 7,
  llvm::SIInstrFlags::P_NORMAL = 1 << 8, llvm::SIInstrFlags::P_INFINITY = 1 << 9
}
 
enum  llvm::AMDGPU::OperandType {
  llvm::AMDGPU::OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_FP32,
  llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32,
  llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64,
  llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
  llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16, llvm::AMDGPU::OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
  llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::AMDGPU::OPERAND_SDWA_VOPC_DST, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_KIMM16
}
 
enum  llvm::SIStackID::StackTypes : uint8_t { llvm::SIStackID::SCRATCH = 0, llvm::SIStackID::SGPR_SPILL = 1 }
 
enum  {
  llvm::SISrcMods::NEG = 1 << 0, llvm::SISrcMods::ABS = 1 << 1, llvm::SISrcMods::SEXT = 1 << 0, llvm::SISrcMods::NEG_HI = ABS,
  llvm::SISrcMods::OP_SEL_0 = 1 << 2, llvm::SISrcMods::OP_SEL_1 = 1 << 3, llvm::SISrcMods::DST_OP_SEL = 1 << 3
}
 
enum  { llvm::SIOutMods::NONE = 0, llvm::SIOutMods::MUL2 = 1, llvm::SIOutMods::MUL4 = 2, llvm::SIOutMods::DIV2 = 3 }
 
enum  { llvm::VGPRIndexMode::SRC0_ENABLE = 1 << 0, llvm::VGPRIndexMode::SRC1_ENABLE = 1 << 1, llvm::VGPRIndexMode::SRC2_ENABLE = 1 << 2, llvm::VGPRIndexMode::DST_ENABLE = 1 << 3 }
 
enum  {
  llvm::AMDGPUAsmVariants::DEFAULT = 0, llvm::AMDGPUAsmVariants::VOP3 = 1, llvm::AMDGPUAsmVariants::SDWA = 2, llvm::AMDGPUAsmVariants::SDWA9 = 3,
  llvm::AMDGPUAsmVariants::DPP = 4
}
 
enum  {
  llvm::AMDGPU::EncValues::SGPR_MIN = 0, llvm::AMDGPU::EncValues::SGPR_MAX = 101, llvm::AMDGPU::EncValues::TTMP_VI_MIN = 112, llvm::AMDGPU::EncValues::TTMP_VI_MAX = 123,
  llvm::AMDGPU::EncValues::TTMP_GFX9_MIN = 108, llvm::AMDGPU::EncValues::TTMP_GFX9_MAX = 123, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN = 128, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX = 192,
  llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX = 208, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN = 240, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX = 248, llvm::AMDGPU::EncValues::LITERAL_CONST = 255,
  llvm::AMDGPU::EncValues::VGPR_MIN = 256, llvm::AMDGPU::EncValues::VGPR_MAX = 511
}
 
enum  llvm::AMDGPU::SendMsg::Id {
  llvm::AMDGPU::SendMsg::ID_UNKNOWN_ = -1, llvm::AMDGPU::SendMsg::ID_INTERRUPT = 1, llvm::AMDGPU::SendMsg::ID_GS, llvm::AMDGPU::SendMsg::ID_GS_DONE,
  llvm::AMDGPU::SendMsg::ID_SYSMSG = 15, llvm::AMDGPU::SendMsg::ID_GAPS_LAST_, llvm::AMDGPU::SendMsg::ID_GAPS_FIRST_ = ID_INTERRUPT, llvm::AMDGPU::SendMsg::ID_SHIFT_ = 0,
  llvm::AMDGPU::SendMsg::ID_WIDTH_ = 4, llvm::AMDGPU::SendMsg::ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
}
 
enum  llvm::AMDGPU::SendMsg::Op {
  llvm::AMDGPU::SendMsg::OP_UNKNOWN_ = -1, llvm::AMDGPU::SendMsg::OP_SHIFT_ = 4, llvm::AMDGPU::SendMsg::OP_GS_NOP = 0, llvm::AMDGPU::SendMsg::OP_GS_CUT,
  llvm::AMDGPU::SendMsg::OP_GS_EMIT, llvm::AMDGPU::SendMsg::OP_GS_EMIT_CUT, llvm::AMDGPU::SendMsg::OP_GS_LAST_, llvm::AMDGPU::SendMsg::OP_GS_FIRST_ = OP_GS_NOP,
  llvm::AMDGPU::SendMsg::OP_GS_WIDTH_ = 2, llvm::AMDGPU::SendMsg::OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_), llvm::AMDGPU::SendMsg::OP_SYS_ECC_ERR_INTERRUPT = 1, llvm::AMDGPU::SendMsg::OP_SYS_REG_RD,
  llvm::AMDGPU::SendMsg::OP_SYS_HOST_TRAP_ACK, llvm::AMDGPU::SendMsg::OP_SYS_TTRACE_PC, llvm::AMDGPU::SendMsg::OP_SYS_LAST_, llvm::AMDGPU::SendMsg::OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
  llvm::AMDGPU::SendMsg::OP_SYS_WIDTH_ = 3, llvm::AMDGPU::SendMsg::OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
}
 
enum  llvm::AMDGPU::SendMsg::StreamId {
  llvm::AMDGPU::SendMsg::STREAM_ID_DEFAULT_ = 0, llvm::AMDGPU::SendMsg::STREAM_ID_LAST_ = 4, llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_ = 8,
  llvm::AMDGPU::SendMsg::STREAM_ID_WIDTH_ = 2, llvm::AMDGPU::SendMsg::STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
}
 
enum  llvm::AMDGPU::Hwreg::Id {
  llvm::AMDGPU::Hwreg::ID_UNKNOWN_ = -1, llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_ = 1, llvm::AMDGPU::Hwreg::ID_MODE = 1, llvm::AMDGPU::Hwreg::ID_STATUS = 2,
  llvm::AMDGPU::Hwreg::ID_TRAPSTS = 3, llvm::AMDGPU::Hwreg::ID_HW_ID = 4, llvm::AMDGPU::Hwreg::ID_GPR_ALLOC = 5, llvm::AMDGPU::Hwreg::ID_LDS_ALLOC = 6,
  llvm::AMDGPU::Hwreg::ID_IB_STS = 7, llvm::AMDGPU::Hwreg::ID_MEM_BASES = 15, llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, llvm::AMDGPU::Hwreg::ID_SYMBOLIC_LAST_ = 16,
  llvm::AMDGPU::Hwreg::ID_SHIFT_ = 0, llvm::AMDGPU::Hwreg::ID_WIDTH_ = 6, llvm::AMDGPU::Hwreg::ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
}
 
enum  llvm::AMDGPU::Hwreg::Offset {
  llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_ = 0, llvm::AMDGPU::Hwreg::OFFSET_SHIFT_ = 6, llvm::AMDGPU::Hwreg::OFFSET_WIDTH_ = 5, llvm::AMDGPU::Hwreg::OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
  llvm::AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE = 16, llvm::AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE = 0
}
 
enum  llvm::AMDGPU::Hwreg::WidthMinusOne {
  llvm::AMDGPU::Hwreg::WIDTH_M1_DEFAULT_ = 31, llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_ = 11, llvm::AMDGPU::Hwreg::WIDTH_M1_WIDTH_ = 5, llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
  llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE = 15, llvm::AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE = 15
}
 
enum  llvm::AMDGPU::Swizzle::Id {
  llvm::AMDGPU::Swizzle::ID_QUAD_PERM = 0, llvm::AMDGPU::Swizzle::ID_BITMASK_PERM, llvm::AMDGPU::Swizzle::ID_SWAP, llvm::AMDGPU::Swizzle::ID_REVERSE,
  llvm::AMDGPU::Swizzle::ID_BROADCAST
}
 
enum  llvm::AMDGPU::Swizzle::EncBits {
  llvm::AMDGPU::Swizzle::QUAD_PERM_ENC = 0x8000, llvm::AMDGPU::Swizzle::QUAD_PERM_ENC_MASK = 0xFF00, llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC = 0x0000, llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC_MASK = 0x8000,
  llvm::AMDGPU::Swizzle::LANE_MASK = 0x3, llvm::AMDGPU::Swizzle::LANE_MAX = LANE_MASK, llvm::AMDGPU::Swizzle::LANE_SHIFT = 2, llvm::AMDGPU::Swizzle::LANE_NUM = 4,
  llvm::AMDGPU::Swizzle::BITMASK_MASK = 0x1F, llvm::AMDGPU::Swizzle::BITMASK_MAX = BITMASK_MASK, llvm::AMDGPU::Swizzle::BITMASK_WIDTH = 5, llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT = 0,
  llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT = 5, llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT = 10
}
 
enum  llvm::AMDGPU::SDWA::SdwaSel {
  llvm::AMDGPU::SDWA::BYTE_0 = 0, llvm::AMDGPU::SDWA::BYTE_1 = 1, llvm::AMDGPU::SDWA::BYTE_2 = 2, llvm::AMDGPU::SDWA::BYTE_3 = 3,
  llvm::AMDGPU::SDWA::WORD_0 = 4, llvm::AMDGPU::SDWA::WORD_1 = 5, llvm::AMDGPU::SDWA::DWORD = 6
}
 
enum  llvm::AMDGPU::SDWA::DstUnused { llvm::AMDGPU::SDWA::UNUSED_PAD = 0, llvm::AMDGPU::SDWA::UNUSED_SEXT = 1, llvm::AMDGPU::SDWA::UNUSED_PRESERVE = 2 }
 
enum  llvm::AMDGPU::SDWA::SDWA9EncValues {
  llvm::AMDGPU::SDWA::SRC_SGPR_MASK = 0x100, llvm::AMDGPU::SDWA::SRC_VGPR_MASK = 0xFF, llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK = 0x80, llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK = 0x7F,
  llvm::AMDGPU::SDWA::SRC_VGPR_MIN = 0, llvm::AMDGPU::SDWA::SRC_VGPR_MAX = 255, llvm::AMDGPU::SDWA::SRC_SGPR_MIN = 256, llvm::AMDGPU::SDWA::SRC_SGPR_MAX = 357,
  llvm::AMDGPU::SDWA::SRC_TTMP_MIN = 364, llvm::AMDGPU::SDWA::SRC_TTMP_MAX = 379
}
 
enum  llvm::AMDGPU::DPP::DppCtrl {
  llvm::AMDGPU::DPP::QUAD_PERM_FIRST = 0, llvm::AMDGPU::DPP::QUAD_PERM_LAST = 0xFF, llvm::AMDGPU::DPP::DPP_UNUSED1 = 0x100, llvm::AMDGPU::DPP::ROW_SHL0 = 0x100,
  llvm::AMDGPU::DPP::ROW_SHL_FIRST = 0x101, llvm::AMDGPU::DPP::ROW_SHL_LAST = 0x10F, llvm::AMDGPU::DPP::DPP_UNUSED2 = 0x110, llvm::AMDGPU::DPP::ROW_SHR0 = 0x110,
  llvm::AMDGPU::DPP::ROW_SHR_FIRST = 0x111, llvm::AMDGPU::DPP::ROW_SHR_LAST = 0x11F, llvm::AMDGPU::DPP::DPP_UNUSED3 = 0x120, llvm::AMDGPU::DPP::ROW_ROR0 = 0x120,
  llvm::AMDGPU::DPP::ROW_ROR_FIRST = 0x121, llvm::AMDGPU::DPP::ROW_ROR_LAST = 0x12F, llvm::AMDGPU::DPP::WAVE_SHL1 = 0x130, llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST = 0x131,
  llvm::AMDGPU::DPP::DPP_UNUSED4_LAST = 0x133, llvm::AMDGPU::DPP::WAVE_ROL1 = 0x134, llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST = 0x135, llvm::AMDGPU::DPP::DPP_UNUSED5_LAST = 0x137,
  llvm::AMDGPU::DPP::WAVE_SHR1 = 0x138, llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST = 0x139, llvm::AMDGPU::DPP::DPP_UNUSED6_LAST = 0x13B, llvm::AMDGPU::DPP::WAVE_ROR1 = 0x13C,
  llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST = 0x13D, llvm::AMDGPU::DPP::DPP_UNUSED7_LAST = 0x13F, llvm::AMDGPU::DPP::ROW_MIRROR = 0x140, llvm::AMDGPU::DPP::ROW_HALF_MIRROR = 0x141,
  llvm::AMDGPU::DPP::BCAST15 = 0x142, llvm::AMDGPU::DPP::BCAST31 = 0x143, llvm::AMDGPU::DPP::DPP_LAST = BCAST31
}
 

Macro Definition Documentation

◆ C_00B848_DEBUG_MODE

#define C_00B848_DEBUG_MODE   0xFFBFFFFF

Definition at line 504 of file SIDefines.h.

◆ C_00B848_DX10_CLAMP

#define C_00B848_DX10_CLAMP   0xFFDFFFFF

Definition at line 501 of file SIDefines.h.

◆ C_00B848_FLOAT_MODE

#define C_00B848_FLOAT_MODE   0xFFF00FFF

Definition at line 495 of file SIDefines.h.

◆ C_00B848_IEEE_MODE

#define C_00B848_IEEE_MODE   0xFF7FFFFF

Definition at line 507 of file SIDefines.h.

◆ C_00B848_PRIORITY

#define C_00B848_PRIORITY   0xFFFFF3FF

Definition at line 492 of file SIDefines.h.

◆ C_00B848_PRIV

#define C_00B848_PRIV   0xFFEFFFFF

Definition at line 498 of file SIDefines.h.

◆ C_00B848_SGPRS

#define C_00B848_SGPRS   0xFFFFFC3F

Definition at line 489 of file SIDefines.h.

◆ C_00B848_VGPRS

#define C_00B848_VGPRS   0xFFFFFFC0

Definition at line 486 of file SIDefines.h.

◆ C_00B84C_EXCP_EN

#define C_00B84C_EXCP_EN

Definition at line 478 of file SIDefines.h.

◆ C_00B84C_EXCP_EN_MSB

#define C_00B84C_EXCP_EN_MSB   0xFFFF9FFF

Definition at line 471 of file SIDefines.h.

◆ C_00B84C_LDS_SIZE

#define C_00B84C_LDS_SIZE   0xFF007FFF

Definition at line 475 of file SIDefines.h.

◆ C_00B84C_SCRATCH_EN

#define C_00B84C_SCRATCH_EN   0xFFFFFFFE

Definition at line 446 of file SIDefines.h.

◆ C_00B84C_TG_SIZE_EN

#define C_00B84C_TG_SIZE_EN   0xFFFFFBFF

Definition at line 464 of file SIDefines.h.

◆ C_00B84C_TGID_X_EN

#define C_00B84C_TGID_X_EN   0xFFFFFF7F

Definition at line 455 of file SIDefines.h.

◆ C_00B84C_TGID_Y_EN

#define C_00B84C_TGID_Y_EN   0xFFFFFEFF

Definition at line 458 of file SIDefines.h.

◆ C_00B84C_TGID_Z_EN

#define C_00B84C_TGID_Z_EN   0xFFFFFDFF

Definition at line 461 of file SIDefines.h.

◆ C_00B84C_TIDIG_COMP_CNT

#define C_00B84C_TIDIG_COMP_CNT   0xFFFFE7FF

Definition at line 467 of file SIDefines.h.

◆ C_00B84C_TRAP_HANDLER

#define C_00B84C_TRAP_HANDLER   0xFFFFFFBF

Definition at line 452 of file SIDefines.h.

◆ C_00B84C_USER_SGPR

#define C_00B84C_USER_SGPR   0xFFFFFFC1

Definition at line 449 of file SIDefines.h.

◆ FP_DENORM_FLUSH_IN

#define FP_DENORM_FLUSH_IN   2

Definition at line 523 of file SIDefines.h.

◆ FP_DENORM_FLUSH_IN_FLUSH_OUT

#define FP_DENORM_FLUSH_IN_FLUSH_OUT   0

Definition at line 521 of file SIDefines.h.

Referenced by getFPMode(), and getFPTernOp().

◆ FP_DENORM_FLUSH_NONE

#define FP_DENORM_FLUSH_NONE   3

Definition at line 524 of file SIDefines.h.

Referenced by getFPMode(), and getFPTernOp().

◆ FP_DENORM_FLUSH_OUT

#define FP_DENORM_FLUSH_OUT   1

Definition at line 522 of file SIDefines.h.

◆ FP_DENORM_MODE_DP

#define FP_DENORM_MODE_DP (   x)    (((x) & 0x3) << 6)

Definition at line 530 of file SIDefines.h.

Referenced by getFPMode().

◆ FP_DENORM_MODE_SP

#define FP_DENORM_MODE_SP (   x)    (((x) & 0x3) << 4)

Definition at line 529 of file SIDefines.h.

Referenced by getFPMode().

◆ FP_ROUND_MODE_DP

#define FP_ROUND_MODE_DP (   x)    (((x) & 0x3) << 2)

Definition at line 519 of file SIDefines.h.

Referenced by BlockData::BlockData(), llvm::createSIModeRegisterPass(), and getFPMode().

◆ FP_ROUND_MODE_SP

#define FP_ROUND_MODE_SP (   x)    ((x) & 0x3)

Definition at line 518 of file SIDefines.h.

Referenced by getFPMode().

◆ FP_ROUND_ROUND_TO_INF

#define FP_ROUND_ROUND_TO_INF   1

Definition at line 512 of file SIDefines.h.

◆ FP_ROUND_ROUND_TO_NEAREST

#define FP_ROUND_ROUND_TO_NEAREST   0

Definition at line 511 of file SIDefines.h.

Referenced by BlockData::BlockData(), and getFPMode().

◆ FP_ROUND_ROUND_TO_NEGINF

#define FP_ROUND_ROUND_TO_NEGINF   2

Definition at line 513 of file SIDefines.h.

◆ FP_ROUND_ROUND_TO_ZERO

#define FP_ROUND_ROUND_TO_ZERO   3

Definition at line 514 of file SIDefines.h.

Referenced by llvm::createSIModeRegisterPass().

◆ G_00B848_DEBUG_MODE

#define G_00B848_DEBUG_MODE (   x)    (((x) >> 22) & 0x1)

Definition at line 503 of file SIDefines.h.

◆ G_00B848_DX10_CLAMP

#define G_00B848_DX10_CLAMP (   x)    (((x) >> 21) & 0x1)

Definition at line 500 of file SIDefines.h.

◆ G_00B848_FLOAT_MODE

#define G_00B848_FLOAT_MODE (   x)    (((x) >> 12) & 0xFF)

Definition at line 494 of file SIDefines.h.

◆ G_00B848_IEEE_MODE

#define G_00B848_IEEE_MODE (   x)    (((x) >> 23) & 0x1)

Definition at line 506 of file SIDefines.h.

◆ G_00B848_PRIORITY

#define G_00B848_PRIORITY (   x)    (((x) >> 10) & 0x03)

Definition at line 491 of file SIDefines.h.

◆ G_00B848_PRIV

#define G_00B848_PRIV (   x)    (((x) >> 20) & 0x1)

Definition at line 497 of file SIDefines.h.

◆ G_00B848_SGPRS

#define G_00B848_SGPRS (   x)    (((x) >> 6) & 0x0F)

Definition at line 488 of file SIDefines.h.

◆ G_00B848_VGPRS

#define G_00B848_VGPRS (   x)    (((x) >> 0) & 0x3F)

Definition at line 485 of file SIDefines.h.

◆ G_00B84C_EXCP_EN

#define G_00B84C_EXCP_EN (   x)    (((x) >> 24) & 0x7F)

Definition at line 477 of file SIDefines.h.

◆ G_00B84C_EXCP_EN_MSB

#define G_00B84C_EXCP_EN_MSB (   x)    (((x) >> 13) & 0x03)

Definition at line 470 of file SIDefines.h.

◆ G_00B84C_LDS_SIZE

#define G_00B84C_LDS_SIZE (   x)    (((x) >> 15) & 0x1FF)

Definition at line 474 of file SIDefines.h.

◆ G_00B84C_SCRATCH_EN

#define G_00B84C_SCRATCH_EN (   x)    (((x) >> 0) & 0x1)

Definition at line 445 of file SIDefines.h.

◆ G_00B84C_TG_SIZE_EN

#define G_00B84C_TG_SIZE_EN (   x)    (((x) >> 10) & 0x1)

Definition at line 463 of file SIDefines.h.

◆ G_00B84C_TGID_X_EN

#define G_00B84C_TGID_X_EN (   x)    (((x) >> 7) & 0x1)

Definition at line 454 of file SIDefines.h.

Referenced by llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ G_00B84C_TGID_Y_EN

#define G_00B84C_TGID_Y_EN (   x)    (((x) >> 8) & 0x1)

Definition at line 457 of file SIDefines.h.

Referenced by llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ G_00B84C_TGID_Z_EN

#define G_00B84C_TGID_Z_EN (   x)    (((x) >> 9) & 0x1)

Definition at line 460 of file SIDefines.h.

Referenced by llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ G_00B84C_TIDIG_COMP_CNT

#define G_00B84C_TIDIG_COMP_CNT (   x)    (((x) >> 11) & 0x03)

Definition at line 466 of file SIDefines.h.

Referenced by llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ G_00B84C_TRAP_HANDLER

#define G_00B84C_TRAP_HANDLER (   x)    (((x) >> 6) & 0x1)

Definition at line 451 of file SIDefines.h.

Referenced by llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ G_00B84C_USER_SGPR

#define G_00B84C_USER_SGPR (   x)    (((x) >> 1) & 0x1F)

Definition at line 448 of file SIDefines.h.

Referenced by llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ R_00B028_SPI_SHADER_PGM_RSRC1_PS

#define R_00B028_SPI_SHADER_PGM_RSRC1_PS   0x00B028

Definition at line 431 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B02C_SPI_SHADER_PGM_RSRC2_PS

#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS   0x00B02C

Definition at line 432 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B128_SPI_SHADER_PGM_RSRC1_VS

#define R_00B128_SPI_SHADER_PGM_RSRC1_VS   0x00B128

Definition at line 434 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B228_SPI_SHADER_PGM_RSRC1_GS

#define R_00B228_SPI_SHADER_PGM_RSRC1_GS   0x00B228

Definition at line 435 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B328_SPI_SHADER_PGM_RSRC1_ES

#define R_00B328_SPI_SHADER_PGM_RSRC1_ES   0x00B328

Definition at line 436 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B428_SPI_SHADER_PGM_RSRC1_HS

#define R_00B428_SPI_SHADER_PGM_RSRC1_HS   0x00B428

Definition at line 437 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B528_SPI_SHADER_PGM_RSRC1_LS

#define R_00B528_SPI_SHADER_PGM_RSRC1_LS   0x00B528

Definition at line 438 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B848_COMPUTE_PGM_RSRC1 [1/2]

#define R_00B848_COMPUTE_PGM_RSRC1   0x00B848

Definition at line 483 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B848_COMPUTE_PGM_RSRC1 [2/2]

#define R_00B848_COMPUTE_PGM_RSRC1   0x00B848

Definition at line 483 of file SIDefines.h.

◆ R_00B84C_COMPUTE_PGM_RSRC2

#define R_00B84C_COMPUTE_PGM_RSRC2   0x00B84C

Definition at line 443 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_00B860_COMPUTE_TMPRING_SIZE

#define R_00B860_COMPUTE_TMPRING_SIZE   0x00B860

Definition at line 532 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_0286CC_SPI_PS_INPUT_ENA

#define R_0286CC_SPI_PS_INPUT_ENA   0x0286CC

Definition at line 480 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_0286D0_SPI_PS_INPUT_ADDR

#define R_0286D0_SPI_PS_INPUT_ADDR   0x0286D0

Definition at line 481 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_0286E8_SPI_TMPRING_SIZE

#define R_0286E8_SPI_TMPRING_SIZE   0x0286E8

Definition at line 535 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_SPILLED_SGPRS

#define R_SPILLED_SGPRS   0x4

Definition at line 538 of file SIDefines.h.

Referenced by getRsrcReg().

◆ R_SPILLED_VGPRS

#define R_SPILLED_VGPRS   0x8

Definition at line 539 of file SIDefines.h.

Referenced by getRsrcReg().

◆ S_00B028_SGPRS

#define S_00B028_SGPRS (   x)    (((x) & 0x0F) << 6)

Definition at line 441 of file SIDefines.h.

Referenced by getRsrcReg().

◆ S_00B028_VGPRS

#define S_00B028_VGPRS (   x)    (((x) & 0x3F) << 0)

Definition at line 440 of file SIDefines.h.

Referenced by getRsrcReg().

◆ S_00B02C_EXTRA_LDS_SIZE

#define S_00B02C_EXTRA_LDS_SIZE (   x)    (((x) & 0xFF) << 8)

Definition at line 433 of file SIDefines.h.

Referenced by getRsrcReg().

◆ S_00B848_DEBUG_MODE

#define S_00B848_DEBUG_MODE (   x)    (((x) & 0x1) << 22)

Definition at line 502 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B848_DX10_CLAMP

#define S_00B848_DX10_CLAMP (   x)    (((x) & 0x1) << 21)

Definition at line 499 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B848_FLOAT_MODE

#define S_00B848_FLOAT_MODE (   x)    (((x) & 0xFF) << 12)

Definition at line 493 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B848_IEEE_MODE

#define S_00B848_IEEE_MODE (   x)    (((x) & 0x1) << 23)

Definition at line 505 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B848_PRIORITY

#define S_00B848_PRIORITY (   x)    (((x) & 0x03) << 10)

Definition at line 490 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B848_PRIV

#define S_00B848_PRIV (   x)    (((x) & 0x1) << 20)

Definition at line 496 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B848_SGPRS

#define S_00B848_SGPRS (   x)    (((x) & 0x0F) << 6)

Definition at line 487 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B848_VGPRS

#define S_00B848_VGPRS (   x)    (((x) & 0x3F) << 0)

Definition at line 484 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_EXCP_EN

#define S_00B84C_EXCP_EN (   x)    (((x) & 0x7F) << 24)

Definition at line 476 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_EXCP_EN_MSB

#define S_00B84C_EXCP_EN_MSB (   x)    (((x) & 0x03) << 13)

Definition at line 469 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_LDS_SIZE

#define S_00B84C_LDS_SIZE (   x)    (((x) & 0x1FF) << 15)

Definition at line 473 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_SCRATCH_EN

#define S_00B84C_SCRATCH_EN (   x)    (((x) & 0x1) << 0)

Definition at line 444 of file SIDefines.h.

Referenced by getRsrcReg(), and hasAnyNonFlatUseOfReg().

◆ S_00B84C_TG_SIZE_EN

#define S_00B84C_TG_SIZE_EN (   x)    (((x) & 0x1) << 10)

Definition at line 462 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_TGID_X_EN

#define S_00B84C_TGID_X_EN (   x)    (((x) & 0x1) << 7)

Definition at line 453 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_TGID_Y_EN

#define S_00B84C_TGID_Y_EN (   x)    (((x) & 0x1) << 8)

Definition at line 456 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_TGID_Z_EN

#define S_00B84C_TGID_Z_EN (   x)    (((x) & 0x1) << 9)

Definition at line 459 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_TIDIG_COMP_CNT

#define S_00B84C_TIDIG_COMP_CNT (   x)    (((x) & 0x03) << 11)

Definition at line 465 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_TRAP_HANDLER

#define S_00B84C_TRAP_HANDLER (   x)    (((x) & 0x1) << 6)

Definition at line 450 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B84C_USER_SGPR

#define S_00B84C_USER_SGPR (   x)    (((x) & 0x1F) << 1)

Definition at line 447 of file SIDefines.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ S_00B860_WAVESIZE

#define S_00B860_WAVESIZE (   x)    (((x) & 0x1FFF) << 12)

Definition at line 533 of file SIDefines.h.

Referenced by getRsrcReg().

◆ S_0286E8_WAVESIZE

#define S_0286E8_WAVESIZE (   x)    (((x) & 0x1FFF) << 12)

Definition at line 536 of file SIDefines.h.

Referenced by getRsrcReg().

Generated on Sun Dec 20 2020 14:01:04 for LLVM by   doxygen 1.8.13