| enum | VecOps {
UPDATE_EXEC_MASK_X,
UPDATE_PREDICATE_X,
WRITE_X,
OMOD_X,
DST_REL_X,
CLAMP_X,
SRC0_X,
SRC0_NEG_X,
SRC0_REL_X,
SRC0_ABS_X,
SRC0_SEL_X,
SRC1_X,
SRC1_NEG_X,
SRC1_REL_X,
SRC1_ABS_X,
SRC1_SEL_X,
PRED_SEL_X,
UPDATE_EXEC_MASK_Y,
UPDATE_PREDICATE_Y,
WRITE_Y,
OMOD_Y,
DST_REL_Y,
CLAMP_Y,
SRC0_Y,
SRC0_NEG_Y,
SRC0_REL_Y,
SRC0_ABS_Y,
SRC0_SEL_Y,
SRC1_Y,
SRC1_NEG_Y,
SRC1_REL_Y,
SRC1_ABS_Y,
SRC1_SEL_Y,
PRED_SEL_Y,
UPDATE_EXEC_MASK_Z,
UPDATE_PREDICATE_Z,
WRITE_Z,
OMOD_Z,
DST_REL_Z,
CLAMP_Z,
SRC0_Z,
SRC0_NEG_Z,
SRC0_REL_Z,
SRC0_ABS_Z,
SRC0_SEL_Z,
SRC1_Z,
SRC1_NEG_Z,
SRC1_REL_Z,
SRC1_ABS_Z,
SRC1_SEL_Z,
PRED_SEL_Z,
UPDATE_EXEC_MASK_W,
UPDATE_PREDICATE_W,
WRITE_W,
OMOD_W,
DST_REL_W,
CLAMP_W,
SRC0_W,
SRC0_NEG_W,
SRC0_REL_W,
SRC0_ABS_W,
SRC0_SEL_W,
SRC1_W,
SRC1_NEG_W,
SRC1_REL_W,
SRC1_ABS_W,
SRC1_SEL_W,
PRED_SEL_W,
IMM_0,
IMM_1,
VEC_COUNT
} |
