| applyDefaultMapping(const OperandsMapper &OpdMapper) | llvm::RegisterBankInfo | static |
| applyMappingImpl(const OperandsMapper &OpdMapper) const override | llvm::X86RegisterBankInfo | virtual |
| constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) | llvm::RegisterBankInfo | static |
| copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const | llvm::RegisterBankInfo | inlinevirtual |
| DefaultMappingID | llvm::RegisterBankInfo | static |
| getInstrAlternativeMappings(const MachineInstr &MI) const override | llvm::X86RegisterBankInfo | virtual |
| getInstrMapping(const MachineInstr &MI) const override | llvm::X86RegisterBankInfo | virtual |
| getInstrMappingImpl(const MachineInstr &MI) const | llvm::RegisterBankInfo | protected |
| getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const | llvm::RegisterBankInfo | inline |
| getInvalidInstructionMapping() const | llvm::RegisterBankInfo | inline |
| getMinimalPhysRegClass(unsigned Reg, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | protected |
| getNumRegBanks() const | llvm::RegisterBankInfo | inline |
| getOperandsMapping(Iterator Begin, Iterator End) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(const SmallVectorImpl< const ValueMapping *> &OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getOperandsMapping(std::initializer_list< const ValueMapping *> OpdsMapping) const | llvm::RegisterBankInfo | protected |
| getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| getPartialMappingIdx(const LLT &Ty, bool isFP) | llvm::X86GenRegisterBankInfo | protectedstatic |
| getRegBank(unsigned ID) | llvm::RegisterBankInfo | inlineprotected |
| getRegBank(unsigned ID) const | llvm::RegisterBankInfo | inline |
| getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const | llvm::RegisterBankInfo | |
| getRegBankFromRegClass(const TargetRegisterClass &RC) const override | llvm::X86RegisterBankInfo | virtual |
| getValueMapping(PartialMappingIdx Idx, unsigned NumOperands) | llvm::X86GenRegisterBankInfo | protectedstatic |
| llvm::RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const | llvm::RegisterBankInfo | protected |
| llvm::RegisterBankInfo::getValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns) const | llvm::RegisterBankInfo | protected |
| InstructionMappings typedef | llvm::RegisterBankInfo | |
| InvalidMappingID | llvm::RegisterBankInfo | static |
| MapOfInstructionMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfOperandsMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfPartialMappings | llvm::RegisterBankInfo | mutableprotected |
| MapOfValueMappings | llvm::RegisterBankInfo | mutableprotected |
| NumRegBanks | llvm::RegisterBankInfo | protected |
| PartialMappingIdx enum name | llvm::X86GenRegisterBankInfo | protected |
| PartMappings | llvm::X86GenRegisterBankInfo | protectedstatic |
| PhysRegMinimalRCs | llvm::RegisterBankInfo | mutableprotected |
| PMI_FP32 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_FP64 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_GPR16 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_GPR32 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_GPR64 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_GPR8 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_None enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_VEC128 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_VEC256 enum value | llvm::X86GenRegisterBankInfo | protected |
| PMI_VEC512 enum value | llvm::X86GenRegisterBankInfo | protected |
| RegBanks | llvm::RegisterBankInfo | protected |
| RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks) | llvm::RegisterBankInfo | protected |
| RegisterBankInfo() | llvm::RegisterBankInfo | inlineprotected |
| ScalarAddx2 | llvm::RegisterBankInfo | |
| ValMappings | llvm::X86GenRegisterBankInfo | protectedstatic |
| ValueMappingIdx enum name | llvm::X86GenRegisterBankInfo | protected |
| VectorAdd | llvm::RegisterBankInfo | |
| VMI_3OpsFp32Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsFp64Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsGpr16Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsGpr32Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsGpr64Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsGpr8Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsVec128Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsVec256Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_3OpsVec512Idx enum value | llvm::X86GenRegisterBankInfo | protected |
| VMI_None enum value | llvm::X86GenRegisterBankInfo | protected |
| X86RegisterBankInfo(const TargetRegisterInfo &TRI) | llvm::X86RegisterBankInfo | |
| ~RegisterBankInfo()=default | llvm::RegisterBankInfo | virtual |
