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LLVM
8.0.1
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This is the complete list of members for llvm::SIRegisterInfo, including all inherited members.
| AMDGPURegisterInfo() | llvm::AMDGPURegisterInfo | |
| eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override | llvm::SIRegisterInfo | |
| eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const | llvm::SIRegisterInfo | |
| findReachingDef(unsigned Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const | llvm::SIRegisterInfo | |
| findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getCalleeSavedRegs(const MachineFunction *MF) const override | llvm::SIRegisterInfo | |
| getCalleeSavedRegsViaCopy(const MachineFunction *MF) const | llvm::SIRegisterInfo | |
| getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override | llvm::SIRegisterInfo | |
| getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override | llvm::SIRegisterInfo | |
| getCSRFirstUseCost() const override | llvm::SIRegisterInfo | inline |
| getEquivalentSGPRClass(const TargetRegisterClass *VRC) const | llvm::SIRegisterInfo | |
| getEquivalentVGPRClass(const TargetRegisterClass *SRC) const | llvm::SIRegisterInfo | |
| getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override | llvm::SIRegisterInfo | |
| getFrameRegister(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getHWRegIndex(unsigned Reg) const | llvm::SIRegisterInfo | inline |
| getMUBUFInstrOffset(const MachineInstr *MI) const | llvm::SIRegisterInfo | |
| getPhysRegClass(unsigned Reg) const | llvm::SIRegisterInfo | |
| getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override | llvm::SIRegisterInfo | |
| getRegAsmName(unsigned Reg) const override | llvm::SIRegisterInfo | |
| getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const | llvm::SIRegisterInfo | |
| getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override | llvm::SIRegisterInfo | |
| getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const | llvm::SIRegisterInfo | |
| getRegUnitPressureSets(unsigned RegUnit) const override | llvm::SIRegisterInfo | |
| getReservedRegs(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getReturnAddressReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getSGPRPressureSet() const | llvm::SIRegisterInfo | inline |
| getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const | llvm::SIRegisterInfo | |
| getSubRegFromChannel(unsigned Channel) | llvm::AMDGPURegisterInfo | static |
| getVGPRPressureSet() const | llvm::SIRegisterInfo | inline |
| hasVGPRs(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | |
| isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override | llvm::SIRegisterInfo | |
| isSGPRClass(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | inline |
| isSGPRClassID(unsigned RCID) const | llvm::SIRegisterInfo | inline |
| isSGPRPressureSet(unsigned SetID) const | llvm::SIRegisterInfo | inline |
| isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const | llvm::SIRegisterInfo | inline |
| isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const | llvm::SIRegisterInfo | |
| isVGPRPressureSet(unsigned SetID) const | llvm::SIRegisterInfo | inline |
| materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override | llvm::SIRegisterInfo | |
| needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override | llvm::SIRegisterInfo | |
| opCanUseInlineConstant(unsigned OpType) const | llvm::SIRegisterInfo | inline |
| opCanUseLiteralConstant(unsigned OpType) const | llvm::SIRegisterInfo | inline |
| requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| requiresFrameIndexScavenging(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| requiresRegisterScavenging(const MachineFunction &Fn) const override | llvm::SIRegisterInfo | |
| requiresVirtualBaseRegisters(const MachineFunction &Fn) const override | llvm::SIRegisterInfo | |
| reservedPrivateSegmentBufferReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| reservedStackPtrOffsetReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| reserveRegisterTuples(BitVector &, unsigned Reg) const | llvm::AMDGPURegisterInfo | |
| resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override | llvm::SIRegisterInfo | |
| restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const | llvm::SIRegisterInfo | |
| shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override | llvm::SIRegisterInfo | |
| shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override | llvm::SIRegisterInfo | |
| SIRegisterInfo(const GCNSubtarget &ST) | llvm::SIRegisterInfo | |
| spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const | llvm::SIRegisterInfo | |
| spillSGPRToSMEM() const | llvm::SIRegisterInfo | inline |
| spillSGPRToVGPR() const | llvm::SIRegisterInfo | inline |
| trackLivenessAfterRegAlloc(const MachineFunction &MF) const override | llvm::SIRegisterInfo |
1.8.13