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LLVM
8.0.1
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This is the complete list of members for llvm::MipsMCCodeEmitter, including all inherited members.
| EmitByte(unsigned char C, raw_ostream &OS) const | llvm::MipsMCCodeEmitter | |
| EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const | llvm::MipsMCCodeEmitter | |
| encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override | llvm::MipsMCCodeEmitter | virtual |
| getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getExprOpValue(const MCExpr *Expr, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getMSAMemEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getRegisterListOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getSizeInsEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getUImm4AndValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const | llvm::MipsMCCodeEmitter | |
| MCCodeEmitter() | llvm::MCCodeEmitter | protected |
| MCCodeEmitter(const MCCodeEmitter &)=delete | llvm::MCCodeEmitter | |
| MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) | llvm::MipsMCCodeEmitter | inline |
| MipsMCCodeEmitter(const MipsMCCodeEmitter &)=delete | llvm::MipsMCCodeEmitter | |
| operator=(const MipsMCCodeEmitter &)=delete | llvm::MipsMCCodeEmitter | |
| llvm::MCCodeEmitter::operator=(const MCCodeEmitter &)=delete | llvm::MCCodeEmitter | |
| reset() | llvm::MCCodeEmitter | inlinevirtual |
| ~MCCodeEmitter() | llvm::MCCodeEmitter | virtual |
| ~MipsMCCodeEmitter() override=default | llvm::MipsMCCodeEmitter |
1.8.13