| adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override | llvm::HexagonSubtarget | |
| enableMachineSchedDefaultSched() const override | llvm::HexagonSubtarget | inline |
| enableMachineScheduler() const override | llvm::HexagonSubtarget | |
| enablePostRAScheduler() const override | llvm::HexagonSubtarget | inline |
| enableSubRegLiveness() const override | llvm::HexagonSubtarget | |
| getAntiDepBreakMode() const override | llvm::HexagonSubtarget | inline |
| getCPUString() const | llvm::HexagonSubtarget | inline |
| getFrameLowering() const override | llvm::HexagonSubtarget | inline |
| getHexagonArchVersion() const | llvm::HexagonSubtarget | inline |
| getHVXElementTypes() const | llvm::HexagonSubtarget | inline |
| getInstrInfo() const override | llvm::HexagonSubtarget | inline |
| getInstrItineraryData() const override | llvm::HexagonSubtarget | inline |
| getL1CacheLineSize() const | llvm::HexagonSubtarget | |
| getL1PrefetchDistance() const | llvm::HexagonSubtarget | |
| getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override | llvm::HexagonSubtarget | |
| getRegisterInfo() const override | llvm::HexagonSubtarget | inline |
| getSelectionDAGInfo() const override | llvm::HexagonSubtarget | inline |
| getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override | llvm::HexagonSubtarget | |
| getTargetLowering() const override | llvm::HexagonSubtarget | inline |
| getTypeAlignment(MVT Ty) const | llvm::HexagonSubtarget | inline |
| getVectorLength() const | llvm::HexagonSubtarget | inline |
| hasMemNoShuf() const | llvm::HexagonSubtarget | inline |
| hasReservedR19() const | llvm::HexagonSubtarget | inline |
| hasV55Ops() const | llvm::HexagonSubtarget | inline |
| hasV55OpsOnly() const | llvm::HexagonSubtarget | inline |
| hasV5Ops() const | llvm::HexagonSubtarget | inline |
| hasV5OpsOnly() const | llvm::HexagonSubtarget | inline |
| hasV60Ops() const | llvm::HexagonSubtarget | inline |
| hasV60OpsOnly() const | llvm::HexagonSubtarget | inline |
| hasV62Ops() const | llvm::HexagonSubtarget | inline |
| hasV62OpsOnly() const | llvm::HexagonSubtarget | inline |
| hasV65Ops() const | llvm::HexagonSubtarget | inline |
| hasV65OpsOnly() const | llvm::HexagonSubtarget | inline |
| hasV66Ops() const | llvm::HexagonSubtarget | inline |
| hasV66OpsOnly() const | llvm::HexagonSubtarget | inline |
| HexagonArchVersion | llvm::HexagonSubtarget | |
| HexagonHVXVersion | llvm::HexagonSubtarget | |
| HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) | llvm::HexagonSubtarget | |
| initializeSubtargetDependencies(StringRef CPU, StringRef FS) | llvm::HexagonSubtarget | |
| isHVXVectorType(MVT VecTy, bool IncludeBool=false) const | llvm::HexagonSubtarget | inline |
| noreturnStackElim() const | llvm::HexagonSubtarget | inline |
| OptLevel | llvm::HexagonSubtarget | |
| ParseSubtargetFeatures(StringRef CPU, StringRef FS) | llvm::HexagonSubtarget | |
| useAA() const override | llvm::HexagonSubtarget | |
| UseBSBScheduling | llvm::HexagonSubtarget | |
| useBSBScheduling() const | llvm::HexagonSubtarget | inline |
| useHVX128BOps() const | llvm::HexagonSubtarget | inline |
| useHVX64BOps() const | llvm::HexagonSubtarget | inline |
| useHVXOps() const | llvm::HexagonSubtarget | inline |
| useLongCalls() const | llvm::HexagonSubtarget | inline |
| useMemops() const | llvm::HexagonSubtarget | inline |
| useNewValueJumps() const | llvm::HexagonSubtarget | inline |
| useNewValueStores() const | llvm::HexagonSubtarget | inline |
| usePackets() const | llvm::HexagonSubtarget | inline |
| usePredicatedCalls() const | llvm::HexagonSubtarget | |
| useSmallData() const | llvm::HexagonSubtarget | inline |
| useZRegOps() const | llvm::HexagonSubtarget | inline |
