LLVM  8.0.1
llvm::HexagonSubtarget Member List

This is the complete list of members for llvm::HexagonSubtarget, including all inherited members.

adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const overridellvm::HexagonSubtarget
enableMachineSchedDefaultSched() const overridellvm::HexagonSubtargetinline
enableMachineScheduler() const overridellvm::HexagonSubtarget
enablePostRAScheduler() const overridellvm::HexagonSubtargetinline
enableSubRegLiveness() const overridellvm::HexagonSubtarget
getAntiDepBreakMode() const overridellvm::HexagonSubtargetinline
getCPUString() constllvm::HexagonSubtargetinline
getFrameLowering() const overridellvm::HexagonSubtargetinline
getHexagonArchVersion() constllvm::HexagonSubtargetinline
getHVXElementTypes() constllvm::HexagonSubtargetinline
getInstrInfo() const overridellvm::HexagonSubtargetinline
getInstrItineraryData() const overridellvm::HexagonSubtargetinline
getL1CacheLineSize() constllvm::HexagonSubtarget
getL1PrefetchDistance() constllvm::HexagonSubtarget
getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const overridellvm::HexagonSubtarget
getRegisterInfo() const overridellvm::HexagonSubtargetinline
getSelectionDAGInfo() const overridellvm::HexagonSubtargetinline
getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const overridellvm::HexagonSubtarget
getTargetLowering() const overridellvm::HexagonSubtargetinline
getTypeAlignment(MVT Ty) constllvm::HexagonSubtargetinline
getVectorLength() constllvm::HexagonSubtargetinline
hasMemNoShuf() constllvm::HexagonSubtargetinline
hasReservedR19() constllvm::HexagonSubtargetinline
hasV55Ops() constllvm::HexagonSubtargetinline
hasV55OpsOnly() constllvm::HexagonSubtargetinline
hasV5Ops() constllvm::HexagonSubtargetinline
hasV5OpsOnly() constllvm::HexagonSubtargetinline
hasV60Ops() constllvm::HexagonSubtargetinline
hasV60OpsOnly() constllvm::HexagonSubtargetinline
hasV62Ops() constllvm::HexagonSubtargetinline
hasV62OpsOnly() constllvm::HexagonSubtargetinline
hasV65Ops() constllvm::HexagonSubtargetinline
hasV65OpsOnly() constllvm::HexagonSubtargetinline
hasV66Ops() constllvm::HexagonSubtargetinline
hasV66OpsOnly() constllvm::HexagonSubtargetinline
HexagonArchVersionllvm::HexagonSubtarget
HexagonHVXVersionllvm::HexagonSubtarget
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)llvm::HexagonSubtarget
initializeSubtargetDependencies(StringRef CPU, StringRef FS)llvm::HexagonSubtarget
isHVXVectorType(MVT VecTy, bool IncludeBool=false) constllvm::HexagonSubtargetinline
noreturnStackElim() constllvm::HexagonSubtargetinline
OptLevelllvm::HexagonSubtarget
ParseSubtargetFeatures(StringRef CPU, StringRef FS)llvm::HexagonSubtarget
useAA() const overridellvm::HexagonSubtarget
UseBSBSchedulingllvm::HexagonSubtarget
useBSBScheduling() constllvm::HexagonSubtargetinline
useHVX128BOps() constllvm::HexagonSubtargetinline
useHVX64BOps() constllvm::HexagonSubtargetinline
useHVXOps() constllvm::HexagonSubtargetinline
useLongCalls() constllvm::HexagonSubtargetinline
useMemops() constllvm::HexagonSubtargetinline
useNewValueJumps() constllvm::HexagonSubtargetinline
useNewValueStores() constllvm::HexagonSubtargetinline
usePackets() constllvm::HexagonSubtargetinline
usePredicatedCalls() constllvm::HexagonSubtarget
useSmallData() constllvm::HexagonSubtargetinline
useZRegOps() constllvm::HexagonSubtargetinline