AMDHSA kernel descriptor definitions. More...

#include <cstddef>
#include <cstdint>

Include dependency graph for AMDHSAKernelDescriptor.h:

This graph shows which files directly or indirectly include this file:

Classes
struct	llvm::amdhsa::kernel_descriptor_t

Namespaces
	llvm
	This class represents lattice values for constants.

	llvm::amdhsa

Macros
#define	offsetof(TYPE, MEMBER) ((size_t)&((TYPE*)0)->MEMBER)

#define	AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH)

#define	AMDHSA_BITS_GET(SRC, MSK) ((SRC & MSK) >> MSK ## _SHIFT)

#define	AMDHSA_BITS_SET(DST, MSK, VAL)

#define	COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)

#define	COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)

#define	KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)

Enumerations
enum	: uint8_t { llvm::amdhsa::FLOAT_ROUND_MODE_NEAR_EVEN = 0, llvm::amdhsa::FLOAT_ROUND_MODE_PLUS_INFINITY = 1, llvm::amdhsa::FLOAT_ROUND_MODE_MINUS_INFINITY = 2, llvm::amdhsa::FLOAT_ROUND_MODE_ZERO = 3 }

enum	: uint8_t { llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_DST = 1, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC = 2, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE = 3 }

enum	: uint8_t { llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X = 0, llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y = 1, llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2, llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3 }

enum	: int32_t { llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) }

enum	: int32_t { llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1) }

enum	: int32_t { llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1), llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) }

Detailed Description

AMDHSA kernel descriptor definitions.

For more information, visit https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor

Definition in file AMDHSAKernelDescriptor.h.

Macro Definition Documentation

◆ AMDHSA_BITS_ENUM_ENTRY

#define AMDHSA_BITS_ENUM_ENTRY	(	NAME,
		SHIFT,
		WIDTH
	)

Value:

NAME ## _SHIFT = (SHIFT),                        \
  NAME ## _WIDTH = (WIDTH),                        \
  NAME = (((1 << (WIDTH)) - 1) << (SHIFT))

Definition at line 30 of file AMDHSAKernelDescriptor.h.

◆ AMDHSA_BITS_GET

#define AMDHSA_BITS_GET	(	SRC,
		MSK
	)	((SRC & MSK) >> MSK ## _SHIFT)

Definition at line 38 of file AMDHSAKernelDescriptor.h.

◆ AMDHSA_BITS_SET

#define AMDHSA_BITS_SET	(	DST,
		MSK,
		VAL
	)

Value:

DST &= ~MSK; \

DST |= ((VAL << MSK ## _SHIFT) & MSK)

Definition at line 43 of file AMDHSAKernelDescriptor.h.

Referenced by llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor(), and getSpecialRegForName().

◆ COMPUTE_PGM_RSRC1

#define COMPUTE_PGM_RSRC1	(	NAME,
		SHIFT,
		WIDTH
	)	AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)

Definition at line 76 of file AMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC2

#define COMPUTE_PGM_RSRC2	(	NAME,
		SHIFT,
		WIDTH
	)	AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)

Definition at line 98 of file AMDHSAKernelDescriptor.h.

◆ KERNEL_CODE_PROPERTY

#define KERNEL_CODE_PROPERTY	(	NAME,
		SHIFT,
		WIDTH
	)	AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)

Definition at line 124 of file AMDHSAKernelDescriptor.h.

◆ offsetof

#define offsetof	(	TYPE,
		MEMBER
	)	((size_t)&((TYPE*)0)->MEMBER)

Definition at line 24 of file AMDHSAKernelDescriptor.h.

Referenced by llvm::AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(), llvm::AppleAcceleratorTable::extract(), llvm::object::ArchiveMemberHeader::getName(), llvm::object::MachOObjectFile::getUuid(), llvm::identify_magic(), isWeak(), and operator new().

Classes

Namespaces

Macros

Enumerations