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LLVM
8.0.1
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This is the complete list of members for llvm::SIInstrInfo, including all inherited members.
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override | llvm::SIInstrInfo | |
| analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const | llvm::SIInstrInfo | |
| areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override | llvm::SIInstrInfo | |
| areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override | llvm::SIInstrInfo | |
| buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const | llvm::SIInstrInfo | |
| buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const | llvm::SIInstrInfo | |
| buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const | llvm::SIInstrInfo | |
| calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const | llvm::SIInstrInfo | |
| canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override | llvm::SIInstrInfo | |
| canReadVGPR(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | |
| canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const | llvm::SIInstrInfo | |
| commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override | llvm::SIInstrInfo | protected |
| commuteOpcode(unsigned Opc) const | llvm::SIInstrInfo | |
| commuteOpcode(const MachineInstr &MI) const | llvm::SIInstrInfo | inline |
| convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const | llvm::SIInstrInfo | |
| convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const | llvm::SIInstrInfo | |
| convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override | llvm::SIInstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override | llvm::SIInstrInfo | |
| CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override | llvm::SIInstrInfo | |
| CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override | llvm::SIInstrInfo | |
| decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::SIInstrInfo | |
| expandPostRAPseudo(MachineInstr &MI) const override | llvm::SIInstrInfo | |
| findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override | llvm::SIInstrInfo | |
| findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const | llvm::SIInstrInfo | |
| FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final | llvm::SIInstrInfo | |
| getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const | llvm::SIInstrInfo | |
| getAddressSpaceForPseudoSourceKind(unsigned Kind) const override | llvm::SIInstrInfo | |
| getBranchDestBlock(const MachineInstr &MI) const override | llvm::SIInstrInfo | |
| getClampMask(const MachineInstr &MI) const | llvm::SIInstrInfo | inline |
| getDefaultRsrcDataFormat() const | llvm::SIInstrInfo | |
| getInstBundleSize(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| getInstSizeInBytes(const MachineInstr &MI) const override | llvm::SIInstrInfo | |
| getKillTerminatorFromPseudo(unsigned Opcode) const | llvm::SIInstrInfo | |
| getMachineCSELookAheadLimit() const override | llvm::SIInstrInfo | inline |
| getMCOpcodeFromPseudo(unsigned Opcode) const | llvm::SIInstrInfo | inline |
| getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const final | llvm::SIInstrInfo | |
| getMovOpcode(const TargetRegisterClass *DstRC) const | llvm::SIInstrInfo | |
| getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | inline |
| getNamedOperand(MachineInstr &MI, unsigned OperandName) const | llvm::SIInstrInfo | |
| getNamedOperand(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | inline |
| getNumWaitStates(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| getOpRegClass(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | |
| getOpSize(uint16_t Opcode, unsigned OpNo) const | llvm::SIInstrInfo | inline |
| getOpSize(const MachineInstr &MI, unsigned OpNo) const | llvm::SIInstrInfo | inline |
| getPreferredSelectRegClass(unsigned Size) const | llvm::SIInstrInfo | |
| getRegisterInfo() const | llvm::SIInstrInfo | inline |
| getScratchRsrcWords23() const | llvm::SIInstrInfo | |
| getSerializableDirectMachineOperandTargetFlags() const override | llvm::SIInstrInfo | |
| getSerializableTargetIndices() const override | llvm::SIInstrInfo | |
| getVALUOp(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| hasAnyModifiersSet(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| hasFPClamp(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| hasFPClamp(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| hasIntClamp(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| hasModifiers(unsigned Opcode) const | llvm::SIInstrInfo | |
| hasModifiersSet(const MachineInstr &MI, unsigned OpName) const | llvm::SIInstrInfo | |
| hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| hasVALU32BitEncoding(unsigned Opcode) const | llvm::SIInstrInfo | |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::SIInstrInfo | |
| insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const | llvm::SIInstrInfo | |
| insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override | llvm::SIInstrInfo | |
| insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const | llvm::SIInstrInfo | |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::SIInstrInfo | |
| insertReturn(MachineBasicBlock &MBB) const | llvm::SIInstrInfo | |
| insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override | llvm::SIInstrInfo | |
| insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const | llvm::SIInstrInfo | |
| insertWaitStates(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const | llvm::SIInstrInfo | |
| isAlwaysGDS(uint16_t Opcode) const | llvm::SIInstrInfo | |
| isBasicBlockPrologue(const MachineInstr &MI) const override | llvm::SIInstrInfo | |
| isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override | llvm::SIInstrInfo | |
| isBufferSMRD(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| isDisableWQM(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isDisableWQM(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isDPP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isDPP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isDS(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isDS(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isEXP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isEXP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isFixedSize(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isFixedSize(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isFLAT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isFLAT(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isFoldableCopy(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| isGather4(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isGather4(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isHighLatencyInstruction(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const | llvm::SIInstrInfo | |
| isInlineConstant(const APInt &Imm) const | llvm::SIInstrInfo | |
| isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const | llvm::SIInstrInfo | |
| isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const | llvm::SIInstrInfo | inline |
| isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const | llvm::SIInstrInfo | inline |
| isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const | llvm::SIInstrInfo | inline |
| isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const | llvm::SIInstrInfo | inline |
| isInlineConstant(const MachineOperand &MO) const | llvm::SIInstrInfo | inline |
| isKillTerminator(unsigned Opcode) | llvm::SIInstrInfo | static |
| isLegalMUBUFImmOffset(unsigned Imm) | llvm::SIInstrInfo | inlinestatic |
| isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const | llvm::SIInstrInfo | |
| isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const | llvm::SIInstrInfo | |
| isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const | llvm::SIInstrInfo | inline |
| isLiteralConstant(const MachineInstr &MI, int OpIdx) const | llvm::SIInstrInfo | inline |
| isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const | llvm::SIInstrInfo | |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::SIInstrInfo | |
| isLowLatencyInstruction(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| isMIMG(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isMIMG(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isMTBUF(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isMTBUF(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isMUBUF(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isMUBUF(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isNonUniformBranchInstr(MachineInstr &Instr) const | llvm::SIInstrInfo | |
| isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const | llvm::SIInstrInfo | |
| isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override | llvm::SIInstrInfo | |
| isSALU(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSALU(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isScalarStore(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isScalarStore(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isScalarUnit(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override | llvm::SIInstrInfo | |
| isSDWA(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSDWA(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSegmentSpecificFLAT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSGPRSpill(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSGPRSpill(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const | llvm::SIInstrInfo | |
| isSMRD(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSMRD(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOP1(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSOP1(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOP2(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSOP2(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOPC(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSOPC(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOPK(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSOPK(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isSOPP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isSOPP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isStackAccess(const MachineInstr &MI, int &FrameIndex) const | llvm::SIInstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::SIInstrInfo | |
| isVALU(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVALU(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVGPRCopy(const MachineInstr &MI) const | llvm::SIInstrInfo | inline |
| isVGPRSpill(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVGPRSpill(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVINTRP(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVINTRP(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVMEM(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVMEM(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOP1(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVOP1(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOP2(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVOP2(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOP3(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVOP3(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOP3P(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVOP3P(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isVOPC(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isVOPC(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| isWQM(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| isWQM(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const | llvm::SIInstrInfo | |
| legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const | llvm::SIInstrInfo | |
| legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const | llvm::SIInstrInfo | |
| legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const | llvm::SIInstrInfo | |
| legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const | llvm::SIInstrInfo | |
| legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const | llvm::SIInstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::SIInstrInfo | |
| materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const | llvm::SIInstrInfo | |
| mayAccessFlatAddressSpace(const MachineInstr &MI) const | llvm::SIInstrInfo | |
| MO_GOTPCREL enum value | llvm::SIInstrInfo | |
| MO_GOTPCREL32 enum value | llvm::SIInstrInfo | |
| MO_GOTPCREL32_HI enum value | llvm::SIInstrInfo | |
| MO_GOTPCREL32_LO enum value | llvm::SIInstrInfo | |
| MO_MASK enum value | llvm::SIInstrInfo | |
| MO_NONE enum value | llvm::SIInstrInfo | |
| MO_REL32 enum value | llvm::SIInstrInfo | |
| MO_REL32_HI enum value | llvm::SIInstrInfo | |
| MO_REL32_LO enum value | llvm::SIInstrInfo | |
| moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const | llvm::SIInstrInfo | |
| pseudoToMCOpcode(int Opcode) const | llvm::SIInstrInfo | |
| readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const | llvm::SIInstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::SIInstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::SIInstrInfo | |
| shouldClusterMemOps(MachineOperand &BaseOp1, MachineOperand &BaseOp2, unsigned NumLoads) const override | llvm::SIInstrInfo | |
| shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override | llvm::SIInstrInfo | |
| SIInstrInfo(const GCNSubtarget &ST) | llvm::SIInstrInfo | explicit |
| sopkIsZext(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| sopkIsZext(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::SIInstrInfo | |
| swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const | llvm::SIInstrInfo | protected |
| TargetOperandFlags enum name | llvm::SIInstrInfo | |
| usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const | llvm::SIInstrInfo | |
| usesFPDPRounding(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| usesFPDPRounding(uint16_t Opcode) const | llvm::SIInstrInfo | inline |
| usesLGKM_CNT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| usesVM_CNT(const MachineInstr &MI) | llvm::SIInstrInfo | inlinestatic |
| verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override | llvm::SIInstrInfo |
1.8.13