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LLVM
8.0.1
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This is the complete list of members for llvm::BPFTargetLowering, including all inherited members.
| addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) | llvm::TargetLoweringBase | inlineprotected |
| AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
| addRegisterClass(MVT VT, const TargetRegisterClass *RC) | llvm::TargetLoweringBase | inlineprotected |
| AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const | llvm::TargetLowering | virtual |
| aggressivelyPreferBuildVectorSources(EVT VecVT) const | llvm::TargetLoweringBase | inlinevirtual |
| alignLoopsWithOptSize() const | llvm::TargetLoweringBase | inlinevirtual |
| allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const | llvm::TargetLoweringBase | |
| allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const | llvm::TargetLoweringBase | inlinevirtual |
| allowTruncateForTailCall(Type *FromTy, Type *ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
| areJTsAllowed(const Function *Fn) const | llvm::TargetLoweringBase | inlinevirtual |
| ArgListTy typedef | llvm::TargetLoweringBase | |
| AsmOperandInfoVector typedef | llvm::TargetLowering | |
| AtomicExpansionKind enum name | llvm::TargetLoweringBase | |
| BooleanContent enum name | llvm::TargetLoweringBase | |
| BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI) | llvm::BPFTargetLowering | explicit |
| BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) const | llvm::TargetLowering | |
| BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode *> &Created) const | llvm::TargetLowering | virtual |
| BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) const | llvm::TargetLowering | |
| C_Memory enum value | llvm::TargetLowering | |
| C_Other enum value | llvm::TargetLowering | |
| C_Register enum value | llvm::TargetLowering | |
| C_RegisterClass enum value | llvm::TargetLowering | |
| C_Unknown enum value | llvm::TargetLowering | |
| canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const | llvm::TargetLoweringBase | inlinevirtual |
| CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const | llvm::TargetLowering | inlinevirtual |
| canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const | llvm::TargetLoweringBase | inlinevirtual |
| canOpTrap(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | virtual |
| combineRepeatedFPDivisors() const | llvm::TargetLowering | inlinevirtual |
| ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const | llvm::TargetLowering | virtual |
| computeKnownBitsForFrameIndex(const SDValue FIOp, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| computeRegisterProperties(const TargetRegisterInfo *TRI) | llvm::TargetLoweringBase | protected |
| ConstraintType enum name | llvm::TargetLowering | |
| ConstraintWeight enum name | llvm::TargetLowering | |
| convertSelectOfConstantsToMath(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| convertSetCCLogicToBitwiseLogic(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const | llvm::TargetLowering | inlinevirtual |
| Custom enum value | llvm::TargetLoweringBase | |
| CW_Best enum value | llvm::TargetLowering | |
| CW_Better enum value | llvm::TargetLowering | |
| CW_Constant enum value | llvm::TargetLowering | |
| CW_Default enum value | llvm::TargetLowering | |
| CW_Good enum value | llvm::TargetLowering | |
| CW_Invalid enum value | llvm::TargetLowering | |
| CW_Memory enum value | llvm::TargetLowering | |
| CW_Okay enum value | llvm::TargetLowering | |
| CW_Register enum value | llvm::TargetLowering | |
| CW_SpecificReg enum value | llvm::TargetLowering | |
| decomposeMulByConstant(EVT VT, SDValue C) const | llvm::TargetLoweringBase | inlinevirtual |
| Disabled enum value | llvm::TargetLoweringBase | |
| emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const | llvm::TargetLoweringBase | inlinevirtual |
| EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override | llvm::BPFTargetLowering | virtual |
| emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | protected |
| emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const | llvm::TargetLowering | inlinevirtual |
| emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
| emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | protected |
| emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | protected |
| enableAggressiveFMAFusion(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| Enabled enum value | llvm::TargetLoweringBase | |
| enableExtLdPromotion() const | llvm::TargetLoweringBase | inline |
| EnableExtLdPromotion | llvm::TargetLoweringBase | protected |
| Expand enum value | llvm::TargetLoweringBase | |
| expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
| ExpandInlineAsm(CallInst *) const | llvm::TargetLowering | inlinevirtual |
| expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const | llvm::TargetLowering | |
| expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const | llvm::TargetLowering | |
| expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const | llvm::TargetLowering | |
| expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const | llvm::TargetLowering | |
| finalizeLowering(MachineFunction &MF) const | llvm::TargetLoweringBase | virtual |
| findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const | llvm::TargetLoweringBase | protectedvirtual |
| functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const | llvm::TargetLowering | inlinevirtual |
| GatherAllAliasesMaxDepth | llvm::TargetLoweringBase | protected |
| getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const | llvm::TargetLoweringBase | inlinevirtual |
| getBooleanContents(bool isVec, bool isFloat) const | llvm::TargetLoweringBase | inline |
| getBooleanContents(EVT Type) const | llvm::TargetLoweringBase | inline |
| getBypassSlowDivWidths() const | llvm::TargetLoweringBase | inline |
| getByValTypeAlignment(Type *Ty, const DataLayout &DL) const | llvm::TargetLoweringBase | virtual |
| getClearCacheBuiltinName() const | llvm::TargetLowering | inlinevirtual |
| getCmpLibcallCC(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getCmpLibcallReturnType() const | llvm::TargetLoweringBase | virtual |
| getCondCodeAction(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| getConstraintType(StringRef Constraint) const | llvm::TargetLowering | virtual |
| getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const | llvm::TargetLoweringBase | protected |
| getDivRefinementSteps(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getExceptionPointerRegister(const Constant *PersonalityFn) const | llvm::TargetLoweringBase | inlinevirtual |
| getExceptionSelectorRegister(const Constant *PersonalityFn) const | llvm::TargetLoweringBase | inlinevirtual |
| getExpandedFixedPointMultiplication(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
| getExtendForAtomicOps() const | llvm::TargetLoweringBase | inlinevirtual |
| getExtendForContent(BooleanContent Content) | llvm::TargetLoweringBase | inlinestatic |
| getFenceOperandTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const | llvm::TargetLoweringBase | inline |
| getFrameIndexTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| getGatherAllAliasesMaxDepth() const | llvm::TargetLoweringBase | inline |
| getHasAlu32() const | llvm::BPFTargetLowering | inline |
| getHasJmpExt() const | llvm::BPFTargetLowering | inline |
| getIndexedLoadAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getIndexedStoreAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
| getInlineAsmMemConstraint(StringRef ConstraintCode) const | llvm::TargetLowering | inlinevirtual |
| getIRStackGuard(IRBuilder<> &IRB) const | llvm::TargetLoweringBase | virtual |
| getJumpBufAlignment() const | llvm::TargetLoweringBase | inline |
| getJumpBufSize() const | llvm::TargetLoweringBase | inline |
| getJumpTableEncoding() const | llvm::TargetLowering | virtual |
| getLibcallCallingConv(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getLibcallName(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
| getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| getMaxAtomicSizeInBitsSupported() const | llvm::TargetLoweringBase | inline |
| getMaxExpandSizeMemcmp(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxGluedStoresPerMemcpy() const | llvm::TargetLoweringBase | inlinevirtual |
| getMaximumJumpTableSize() const | llvm::TargetLoweringBase | |
| getMaxStoresPerMemcpy(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxStoresPerMemmove(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxStoresPerMemset(bool OptSize) const | llvm::TargetLoweringBase | inline |
| getMaxSupportedInterleaveFactor() const | llvm::TargetLoweringBase | inlinevirtual |
| getMemcmpEqZeroLoadsPerBlock() const | llvm::TargetLoweringBase | inlinevirtual |
| getMinCmpXchgSizeInBits() const | llvm::TargetLoweringBase | inline |
| getMinFunctionAlignment() const | llvm::TargetLoweringBase | inline |
| getMinimumJumpTableDensity(bool OptForSize) const | llvm::TargetLoweringBase | |
| getMinimumJumpTableEntries() const | llvm::TargetLoweringBase | virtual |
| getMinStackArgumentAlignment() const | llvm::TargetLoweringBase | inline |
| getMMOFlags(const Instruction &I) const | llvm::TargetLowering | inlinevirtual |
| getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const | llvm::TargetLowering | virtual |
| getNumRegisters(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getOperationAction(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const | llvm::TargetLowering | virtual |
| getPointerTy(const DataLayout &DL, uint32_t AS=0) const | llvm::TargetLoweringBase | inline |
| getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const | llvm::TargetLowering | inlinevirtual |
| getPredictableBranchThreshold() const | llvm::TargetLoweringBase | virtual |
| getPreferredVectorAction(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getPrefFunctionAlignment() const | llvm::TargetLoweringBase | inline |
| getPrefLoopAlignment(MachineLoop *ML=nullptr) const | llvm::TargetLoweringBase | inlinevirtual |
| getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const | llvm::TargetLowering | inlinevirtual |
| getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const | llvm::TargetLowering | inlinevirtual |
| getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getRegClassFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override | llvm::BPFTargetLowering | virtual |
| getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
| getRegisterType(MVT VT) const | llvm::TargetLoweringBase | inline |
| getRegisterType(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getRepRegClassCostFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getRepRegClassFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| getSafeStackPointerLocation(IRBuilder<> &IRB) const | llvm::TargetLoweringBase | virtual |
| getScalarShiftAmountTy(const DataLayout &, EVT) const override | llvm::BPFTargetLowering | virtual |
| getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const | llvm::TargetLoweringBase | inlinevirtual |
| getSchedulingPreference() const | llvm::TargetLoweringBase | inline |
| getSchedulingPreference(SDNode *) const | llvm::TargetLoweringBase | inlinevirtual |
| getScratchRegisters(CallingConv::ID CC) const | llvm::TargetLowering | inlinevirtual |
| getSDagStackGuard(const Module &M) const | llvm::TargetLoweringBase | virtual |
| getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override | llvm::BPFTargetLowering | virtual |
| getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const | llvm::TargetLoweringBase | |
| getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
| getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const | llvm::TargetLowering | virtual |
| getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const | llvm::TargetLowering | inlinevirtual |
| getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
| getSSPStackGuardCheck(const Module &M) const | llvm::TargetLoweringBase | virtual |
| getStackPointerRegisterToSaveRestore() const | llvm::TargetLoweringBase | inline |
| getStackProbeSymbolName(MachineFunction &MF) const | llvm::TargetLoweringBase | inlinevirtual |
| getStrictFPOperationAction(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTargetMachine() const | llvm::TargetLoweringBase | inline |
| getTargetNodeName(unsigned Opcode) const override | llvm::BPFTargetLowering | virtual |
| getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const | llvm::TargetLoweringBase | inlinevirtual |
| getTruncStoreAction(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| getTypeAction(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeAction(MVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const | llvm::TargetLowering | inlinevirtual |
| getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const | llvm::TargetLoweringBase | |
| getTypeToExpandTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeToPromoteTo(unsigned Op, MVT VT) const | llvm::TargetLoweringBase | inline |
| getTypeToTransformTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
| getVaListSizeInBits(const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
| getValueTypeActions() const | llvm::TargetLoweringBase | inline |
| getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const | llvm::TargetLowering | |
| getVectorIdxTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
| getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const | llvm::TargetLoweringBase | |
| getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const | llvm::TargetLoweringBase | inlinevirtual |
| HandleByVal(CCState *, unsigned &, unsigned) const | llvm::TargetLowering | inlinevirtual |
| hasAndNot(SDValue X) const | llvm::TargetLoweringBase | inlinevirtual |
| hasAndNotCompare(SDValue Y) const | llvm::TargetLoweringBase | inlinevirtual |
| hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| hasBitPreservingFPLogic(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| hasExtractBitsInsn() const | llvm::TargetLoweringBase | inline |
| hasFastEqualityCompare(unsigned NumBits) const | llvm::TargetLoweringBase | inlinevirtual |
| hasFloatingPointExceptions() const | llvm::TargetLoweringBase | inline |
| hasMultipleConditionRegisters() const | llvm::TargetLoweringBase | inline |
| hasPairedLoad(EVT, unsigned &) const | llvm::TargetLoweringBase | inlinevirtual |
| hasStandaloneRem(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| hasTargetDAGCombine(ISD::NodeType NT) const | llvm::TargetLoweringBase | inline |
| hasVectorBlend() const | llvm::TargetLoweringBase | inlinevirtual |
| IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const | llvm::TargetLowering | |
| initActions() | llvm::TargetLoweringBase | protected |
| initializeSplitCSR(MachineBasicBlock *Entry) const | llvm::TargetLowering | inlinevirtual |
| insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const | llvm::TargetLowering | inlinevirtual |
| insertSSPDeclarations(Module &M) const | llvm::TargetLoweringBase | virtual |
| InstructionOpcodeToISD(unsigned Opcode) const | llvm::TargetLoweringBase | |
| isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const | llvm::TargetLoweringBase | inlinevirtual |
| isCheapToSpeculateCtlz() const | llvm::TargetLoweringBase | inlinevirtual |
| isCheapToSpeculateCttz() const | llvm::TargetLoweringBase | inlinevirtual |
| isCommutativeBinOp(unsigned Opcode) const | llvm::TargetLoweringBase | inlinevirtual |
| isCondCodeLegal(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
| isConstFalseVal(const SDNode *N) const | llvm::TargetLowering | |
| isConstTrueVal(const SDNode *N) const | llvm::TargetLowering | |
| isCtlzFast() const | llvm::TargetLoweringBase | inlinevirtual |
| isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const | llvm::TargetLowering | inlinevirtual |
| isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const | llvm::TargetLowering | inlinevirtual |
| IsDesirableToPromoteOp(SDValue, EVT &) const | llvm::TargetLowering | inlinevirtual |
| isDesirableToTransformToIntegerOp(unsigned, EVT) const | llvm::TargetLowering | inlinevirtual |
| isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const | llvm::TargetLowering | |
| isExtFree(const Instruction *I) const | llvm::TargetLoweringBase | inline |
| isExtFreeImpl(const Instruction *I) const | llvm::TargetLoweringBase | inlineprotectedvirtual |
| isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const | llvm::TargetLoweringBase | inlinevirtual |
| isFAbsFree(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFMAFasterThanFMulAndFAdd(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFNegFree(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPExtFree(EVT DestVT, EVT SrcVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFPImmLegal(const APFloat &, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isFsqrtCheap(SDValue X, SelectionDAG &DAG) const | llvm::TargetLoweringBase | inlinevirtual |
| isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const | llvm::TargetLowering | virtual |
| isIndexedLoadLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isIndexedStoreLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
| isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const | llvm::TargetLowering | |
| isIntDivCheap(EVT VT, AttributeList Attr) const | llvm::TargetLoweringBase | inlinevirtual |
| isJumpExpensive() const | llvm::TargetLoweringBase | inline |
| isJumpTableRelative() const | llvm::TargetLoweringBase | inlinevirtual |
| isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| isLegalAddImmediate(int64_t) const | llvm::TargetLoweringBase | inlinevirtual |
| isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const | llvm::TargetLoweringBase | virtual |
| isLegalICmpImmediate(int64_t) const | llvm::TargetLoweringBase | inlinevirtual |
| isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const | llvm::TargetLoweringBase | protected |
| isLegalStoreImmediate(int64_t Value) const | llvm::TargetLoweringBase | inlinevirtual |
| isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const | llvm::TargetLoweringBase | inlinevirtual |
| isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isNarrowingProfitable(EVT, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const | llvm::TargetLoweringBase | inlinevirtual |
| isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override | llvm::BPFTargetLowering | virtual |
| isOperationCustom(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationExpand(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegal(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrCustom(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isOperationLegalOrPromote(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
| isPositionIndependent() const | llvm::TargetLowering | |
| isPredictableSelectExpensive() const | llvm::TargetLoweringBase | inline |
| isProfitableToHoist(Instruction *I) const | llvm::TargetLoweringBase | inlinevirtual |
| isSafeMemOpType(MVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isSDNodeAlwaysUniform(const SDNode *N) const | llvm::TargetLowering | inlinevirtual |
| isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const | llvm::TargetLowering | inlinevirtual |
| isSelectSupported(SelectSupportKind) const | llvm::TargetLoweringBase | inlinevirtual |
| isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isShuffleMaskLegal(ArrayRef< int >, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isSlowDivBypassed() const | llvm::TargetLoweringBase | inline |
| isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const | llvm::TargetLoweringBase | inlinevirtual |
| isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const | llvm::TargetLoweringBase | inlinevirtual |
| isTruncateFree(Type *FromTy, Type *ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isTruncateFree(EVT FromVT, EVT ToVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isTruncStoreLegal(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
| isTypeDesirableForOp(unsigned, EVT VT) const | llvm::TargetLowering | inlinevirtual |
| isTypeLegal(EVT VT) const | llvm::TargetLoweringBase | inline |
| isUsedByReturnOnly(SDNode *, SDValue &) const | llvm::TargetLowering | inlinevirtual |
| isVectorClearMaskLegal(ArrayRef< int >, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| isVectorLoadExtDesirable(SDValue ExtVal) const | llvm::TargetLoweringBase | inlinevirtual |
| isVectorShiftByScalarCheap(Type *Ty) const | llvm::TargetLoweringBase | inlinevirtual |
| isZExtFree(Type *FromTy, Type *ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isZExtFree(EVT FromTy, EVT ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
| isZExtFree(SDValue Val, EVT VT2) const | llvm::TargetLoweringBase | inlinevirtual |
| Legal enum value | llvm::TargetLoweringBase | |
| LegalizeAction enum name | llvm::TargetLoweringBase | |
| LegalizeKind typedef | llvm::TargetLoweringBase | |
| LegalizeTypeAction enum name | llvm::TargetLoweringBase | |
| LibCall enum value | llvm::TargetLoweringBase | |
| LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| LowerCallTo(CallLoweringInfo &CLI) const | llvm::TargetLowering | |
| lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const | llvm::TargetLowering | |
| LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const | llvm::TargetLowering | inlinevirtual |
| lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const | llvm::TargetLoweringBase | inlinevirtual |
| lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const | llvm::TargetLoweringBase | inlinevirtual |
| lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const | llvm::TargetLoweringBase | inlinevirtual |
| LowerOperation(SDValue Op, SelectionDAG &DAG) const override | llvm::BPFTargetLowering | virtual |
| LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
| LowerXConstraint(EVT ConstraintVT) const | llvm::TargetLowering | virtual |
| makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const | llvm::TargetLowering | |
| markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const | llvm::TargetLoweringBase | inlinevirtual |
| MaxGluedStoresPerMemcpy | llvm::TargetLoweringBase | protected |
| MaxLoadsPerMemcmp | llvm::TargetLoweringBase | protected |
| MaxLoadsPerMemcmpOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemcpy | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemcpyOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemmove | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemmoveOptSize | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemset | llvm::TargetLoweringBase | protected |
| MaxStoresPerMemsetOptSize | llvm::TargetLoweringBase | protected |
| mayBeEmittedAsTailCall(const CallInst *) const | llvm::TargetLowering | inlinevirtual |
| mergeStoresAfterLegalization() const | llvm::TargetLoweringBase | inlinevirtual |
| MulExpansionKind enum name | llvm::TargetLoweringBase | |
| needsFixedCatchObjects() const | llvm::TargetLoweringBase | inlinevirtual |
| operator=(const TargetLowering &)=delete | llvm::TargetLowering | |
| llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=delete | llvm::TargetLoweringBase | |
| parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const | llvm::TargetLowering | |
| ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const | llvm::TargetLowering | virtual |
| PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::TargetLowering | virtual |
| PredictableSelectIsExpensive | llvm::TargetLoweringBase | protected |
| preferShiftsToClearExtremeBits(SDValue X) const | llvm::TargetLoweringBase | inlinevirtual |
| prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
| Promote enum value | llvm::TargetLoweringBase | |
| rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
| ReciprocalEstimate enum name | llvm::TargetLoweringBase | |
| reduceSelectOfFPConstantLoads(bool IsFPSetCC) const | llvm::TargetLoweringBase | inlinevirtual |
| ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const | llvm::TargetLowering | inlinevirtual |
| ScalarCondVectorVal enum value | llvm::TargetLoweringBase | |
| scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const | llvm::TargetLowering | |
| scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const | llvm::TargetLowering | |
| ScalarValSelect enum value | llvm::TargetLoweringBase | |
| SelectSupportKind enum name | llvm::TargetLoweringBase | |
| setBooleanContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
| setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) | llvm::TargetLoweringBase | inlineprotected |
| setBooleanVectorContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
| setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) | llvm::TargetLoweringBase | inline |
| setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setHasExtractBitsInsn(bool hasExtractInsn=true) | llvm::TargetLoweringBase | inlineprotected |
| setHasFloatingPointExceptions(bool FPExceptions=true) | llvm::TargetLoweringBase | inlineprotected |
| setHasMultipleConditionRegisters(bool hasManyRegs=true) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setJumpBufAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setJumpBufSize(unsigned Size) | llvm::TargetLoweringBase | inlineprotected |
| setJumpIsExpensive(bool isExpensive=true) | llvm::TargetLoweringBase | protected |
| setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) | llvm::TargetLoweringBase | inline |
| setLibcallName(RTLIB::Libcall Call, const char *Name) | llvm::TargetLoweringBase | inline |
| setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
| setMaximumJumpTableSize(unsigned) | llvm::TargetLoweringBase | protected |
| setMinCmpXchgSizeInBits(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
| setMinFunctionAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setMinimumJumpTableEntries(unsigned Val) | llvm::TargetLoweringBase | protected |
| setMinStackArgumentAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
| setPrefFunctionAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setPrefLoopAlignment(unsigned Align) | llvm::TargetLoweringBase | inlineprotected |
| setSchedulingPreference(Sched::Preference Pref) | llvm::TargetLoweringBase | inlineprotected |
| setStackPointerRegisterToSaveRestore(unsigned R) | llvm::TargetLoweringBase | inlineprotected |
| setSupportsUnalignedAtomics(bool UnalignedSupported) | llvm::TargetLoweringBase | inlineprotected |
| setTargetDAGCombine(ISD::NodeType NT) | llvm::TargetLoweringBase | inlineprotected |
| setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
| setUseUnderscoreLongJmp(bool Val) | llvm::TargetLoweringBase | inlineprotected |
| setUseUnderscoreSetJmp(bool Val) | llvm::TargetLoweringBase | inlineprotected |
| shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldConsiderGEPOffsetSplit() const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicLoadInIR(LoadInst *LI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicRMWInIR(AtomicRMWInst *) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandAtomicStoreInIR(StoreInst *SI) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldFoldShiftPairToMask(const SDNode *N, CombineLevel Level) const | llvm::TargetLowering | inlinevirtual |
| shouldInsertFencesForAtomic(const Instruction *I) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldScalarizeBinop(SDValue VecOp) const | llvm::TargetLoweringBase | inlinevirtual |
| ShouldShrinkFPConstant(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldSplatInsEltVarIndex(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const | llvm::TargetLoweringBase | inlinevirtual |
| shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const | llvm::TargetLoweringBase | inlinevirtual |
| ShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
| ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
| SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
| SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
| SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
| SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const | llvm::TargetLowering | virtual |
| SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const | llvm::TargetLowering | |
| softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const | llvm::TargetLowering | |
| storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const | llvm::TargetLoweringBase | inlinevirtual |
| supportSplitCSR(MachineFunction *MF) const | llvm::TargetLowering | inlinevirtual |
| supportsUnalignedAtomics() const | llvm::TargetLoweringBase | inline |
| supportSwiftError() const | llvm::TargetLowering | inlinevirtual |
| TargetLowering(const TargetLowering &)=delete | llvm::TargetLowering | |
| TargetLowering(const TargetMachine &TM) | llvm::TargetLowering | explicit |
| TargetLoweringBase(const TargetMachine &TM) | llvm::TargetLoweringBase | explicit |
| TargetLoweringBase(const TargetLoweringBase &)=delete | llvm::TargetLoweringBase | |
| targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const | llvm::TargetLowering | inlinevirtual |
| TypeExpandFloat enum value | llvm::TargetLoweringBase | |
| TypeExpandInteger enum value | llvm::TargetLoweringBase | |
| TypeLegal enum value | llvm::TargetLoweringBase | |
| TypePromoteFloat enum value | llvm::TargetLoweringBase | |
| TypePromoteInteger enum value | llvm::TargetLoweringBase | |
| TypeScalarizeVector enum value | llvm::TargetLoweringBase | |
| TypeSoftenFloat enum value | llvm::TargetLoweringBase | |
| TypeSplitVector enum value | llvm::TargetLoweringBase | |
| TypeWidenVector enum value | llvm::TargetLoweringBase | |
| UndefinedBooleanContent enum value | llvm::TargetLoweringBase | |
| Unspecified enum value | llvm::TargetLoweringBase | |
| unwrapAddress(SDValue N) const | llvm::TargetLowering | inlinevirtual |
| useLoadStackGuardNode() const | llvm::TargetLowering | inlinevirtual |
| useSoftFloat() const | llvm::TargetLoweringBase | inlinevirtual |
| useStackGuardXorFP() const | llvm::TargetLoweringBase | inlinevirtual |
| usesUnderscoreLongJmp() const | llvm::TargetLoweringBase | inline |
| usesUnderscoreSetJmp() const | llvm::TargetLoweringBase | inline |
| ValueTypeActions | llvm::TargetLoweringBase | protected |
| VectorMaskSelect enum value | llvm::TargetLoweringBase | |
| verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const | llvm::TargetLowering | |
| ZeroOrNegativeOneBooleanContent enum value | llvm::TargetLoweringBase | |
| ZeroOrOneBooleanContent enum value | llvm::TargetLoweringBase | |
| ~TargetLoweringBase()=default | llvm::TargetLoweringBase | virtual |
1.8.13